Overlapped Subarray Segmentation : an Efficient Test Method for Cellular Arrays

This paper presents a new test approach that is suitable for repetitive structures such as cellular arrays. As such, it is directly applicable to most arithmetic circuits which are generally quite regular. It is based on exhaustive testing of overlapping segments of the array. This approach detects bridging faults in addition to stuck-at faults. Such bridging faults are a significant problem in arithmetic circuits. The ability to detect arbitrary faults involving any cells within a designer selected distance (i.e., the diameter of the subset that is exhaustively tested) is unique to this testing approach. The high coverage of the proposed technique makes it attractive for testing current VLSI and future WSI arrays.

ith the ever growing complexity of computer systems, test design and implementation has become a major stumbling block in the quest to de- velop and produce complex circuits at a reasonable cost.Current test generation algorithms [1]- [4] are confined to heuristics and require a prohibitive amount of design effort and test time for current VLSI circuits, even for very limited stuck logic level fault models (where faults are assumed to cause a signal line to be stuck at either a logic ONE or a logic ZERO).Testing is currently recognized as a very difficult problem for VLSI, and is expected to become even more of a problem in the future for WSI and ULSI due to the trend toward increased logic complexity and limited package pin counts.
It has been known for some time [5]- [13] that integrated circuits may display bridging faults where one cell incorrectly affects the logic values in a dif- ferent (but generally physically adjacent) cell.Early work on bridging faults [5] makes the assumption that bridging faults occur where two or more leads in a logic network are connected accidentally and that wired logic (i.e., either a wired OR a wired AND depending on the circuit technology) is performed at the connection.In CMOS bridging faults may not create an unwanted wired OR or wired AND gate, but may produce a signal that causes both the nMOS and pMOS networks in a gate to conduct simulta- neously.The resulting signal level may be interpreted by succeeding circuits as a logic ZERO, a logic ONE, or both.Such behavior may be detected by moni- toring the circuit current while testing [10], [11].
It was reported by Shen et al. [12] that in the design of an array multiplier, "the most prominent fault type is the bridging faults (30 percent)."Array mul- tiplier production experience confirms the existence of bridging faults between adjacent cells in both bi- polar [13] and CMOS implementations.
Although the problem of detecting bridging faults might seem to be similar to the problem of detecting pattern sensitive faults in memories [14], there is greater similarity between bridging faults in logic ar- rays and coupling faults in memories [15].

This paper follows conventions established in
McCluskey [16] by assuming the cells to be combi- national and further assuming that they remain com- binational when faulty so that exhaustive testing of a group of cells will detect any bridging faults be- tween cells in that group.Stuck open and stuck closed faults will be detected if they produce com- binational errors.The basic approach is to partition the logic array into subarrays that can be tested ex- haustively.Unlike the approach in McCluskey and arrays so that bridging faults at the edges of subarrays are detected.
Most conventional testing methods which are de- signed to detect stuck logic levels fail to detect bridg- ing faults.This paper introduces a testing technique called overlapped subarray testing, which employs exhaustive testing of overlapping subarrays of physically adjacent cells.This approach is capable of de- tecting most static fault types including bridging faults.Formulas giving the number of subarrays that must be tested for arbitrary array and segment sizes are derived.Overlapped subarray testing is directly applicable to "bit-slice" structures that are fre- quently employed in realizing arithmetic functions.An example of applying this approach to the testing of a fully parallel array multiplier is given.
After introducing our notation, definitions, and the model, the proposed testing method is described, and the formula for the test length as a function of array and subarray sizes and subarray test length is derived.Next, some practical issues are discussed and the effectiveness of the proposed technique is demonstrated by applying it to an array multiplier.

DEFINITIONS
The following basic concepts underlie the overlapped subarray segmentation approach: A cell is a combinational logic block that is rep- licated in one or more dimensions with regular in- terconnection to create an array.
An intercell bridging fault is a fault where one cell affects another cell to produce an erroneous output.
Bridging span, Span (x, y) is the largest (x, y)   distance between two cells which may interact caus- ing a bridging fault.
Segmentation is the process of dividing an array into subarrays.A segment P(x, y) of an array is a rectangular subarray of x by y contiguous cells.Two segments, P(x, y) and P(x, y), overlap if they have one or more cells in common.
A test vector is a pattern of inputs applied to a circuit to determine the presence or absence of faults.
A cell test is an application of a b-bit test vector to the b inputs of a cell and comparison of the cell outputs with the correct outputs.
An exhaustive cell test is the application of all 2 b distinct cell tests to a cell.
A segment test is the application of an input test vector to a segment of size x cells by y cells and comparison of the cells' outputs with the correct out- puts.
An exhaustive segment test is the application of all distinct input test vectors to a segment of size x by y and comparison with the correct outputs.For a segment of n by ny cells with b inputs, the segment test will include no more than 2 bxy tests.
The test coverage is the fraction of a given class of faults that is detected by specific test.It is assumed that an exhaustive test achieves 100% test coverage of the combinational faults.NOTATION N is the total number of cells.nx, ny is the number of cells in the array along X and Y coordinates, respectively.
(x, y) is the segment size.P(x, y) is the i-th segment of size x cells by y cells.
O(P, P) is the region common to segments P(x, y) and P(x, y).p(x, y) is the number of segments of size x cells by y cells.
Ox(Pi, Pj) is the number of elements in one row of o(e , Oy(Pi, Pj) is the number of elements in one column of o(e, P).
t(x, y) is the number of test vectors required to test an x cell by y cell segment.When there are rn inputs for the x cell by y cell segment fix, y) 2m.
t[x, y, o, Oy] is the number of test vectors required to test the entire array for x cell by y cell segments with incremental overlap Ox, Or. Figure 1 illustrates an example of overlapping seg- ments.Here P(2, 3) and Pi(2, 3) overlap in O(P, P), a one cell by three cell region.Thus, Ox(P, Pi) is one and Oy(ei, Pj) is three.For this example p(x, y) is six.

THE FAULT MODEL
The general fault model, introduced here, assumes that any fault within a segment Pg(x, y) can be de- tected by applying a segment test.This is done by applying an exhaustive segment test that applies all 2" input patterns on the n inputs to the segment.This test achieves 100% coverage of the segment for stuck capability may be needed to detect bridging faults in CMOS).
In general, it is desirable to apply an exhaustive test to the smallest segment for which bridging faults have been observed.Often bridging occurs between adjacent cells or between adjacent layers of metal- lization [18] and a 2 by 2 cell segment will be ade- quate.Overlapping segments of size (x, y) may re- place segments of larger size without sacrifice in test coverage as long as all bridging faults have spans of less than x, y.

OVERLAPPED SUBARRAY TESTING OF 2-DIMENSIONAL ARRAYS
For a two-dimensional cellular array, the overlap process can be viewed as successive tiling with in- cremental displacement in a raster scan format which is analogous to beam motion for a video display.The incremental x-overlap Ox Ox(ei, Pi+ 1) is the over- lap between adjacent segments within a row along the X axis.Similarly, the incremental y-overlap O y is the overlap between adjacent segments within a col- umn along the Y axis.This section provides a pro- cedure to optimize the array test length t[x, y, Ox, Oy] with respect to a given Span(x, y).Span(x, y) is a crucial design parameter that may be assumed a priori or derived through experience.For logic arrays bridging has been observed primarily between adjacent cells.Certainly technology, fea- ture size and layout geometry can provide valuable guidance for an initial Span(x, y) which may be re- fined based on observation of faulty circuits.
The total number of tests required for a given cir- cuit (system) is a function of the length of the seg- ment test and the number of segments.The length of the segment test increases as the segment becomes larger.The number of segments decreases as the segment size increases and increases as the amount of overlap increases.
The number of distinct segments of width x within a row is p(x),

p(x)
Similarly the number of distinct segments of height y within a column is p(y), Then the total number of segments p(x, y) for the two-dimensional array is p(x,y) =p(x)p(y)= ov Since the number of test vectors required to test a segment is t(x, y), the total number of test vectors for a comprehensive test is equal to t[x, y, Ox, Oy] p(X, y)t(x, y) y)   x-Ox y Oy (1) Since t(x, y), the number of tests for an x cell by y cell (with b inputs per cell) segment, is less than or equal to 2 xy (for an exhaustive test), the maximum number of tests is bounded by /max(X, y) p(x, y) 2 xy (2) Equations ( 1) and (2) allow us to construct a test which requires fewer test vectors than naive exhaus- tive test of the entire array.Of course, testing using segments of size (x, y) cannot detect bridging faults with Span(a, b) with a > x or b > y.Since exhaustive test of each x by y segment is assumed to give full coverage of that segment, overlapping subarrays with (Ox, Oy) (x 1, y -1) will give full coverage of the array with respect to Span(a, b) with a -< x and b<_y.
In some situations it may be possible to reduce the number of required test vectors by minimizing the overlap of adjacent (both horizontally and vertically) segments.If for example a four by four cell segment is used, displacing adjacent segments by two cells will reduce the test vector count by a factor of four.
This approach of a large segment size (x, y) and minimal overlap will not detect all faults with Span(x, y).

EXAMPLES
An example is presented in this Section to illustrate the application of overlapped subarray segmenta- tion.
Examination of a parallel multiplier illustrates the application of these proposed concepts to a two di- mensional logic array.The structure of an array mul- tiplier for a pair of N-bit positive numbers is shown by the block diagram of Figure 2 and the photomi- crograph of Figure 3 in a regular rectangular array.Commercial array multipliers negate some inputs to the cells along the left and bottom edges of the array to implement two's complement arithmetic [19], but retain the basic structure consisting of a rectangular cellular array.
Exhaustively testing an N by N array multiplier requires 2 2N+1 test vectors since there are 2N + 1 inputs (N bits each for the two operands and one bit for the round control).Although exhaustive testing has been used for multipliers as large as 16 by 16   (where 8.6 x 10 test vectors are required), it is not feasible for larger multipliers.
An alternative approach is to exhaustively test each of the N 2 + N-1 cells.Because the gate cells have two inputs, four test vectors are required to exhaustively test them.Similarly, the half adder cells have three inputs and require eight test vectors and the full adder cells have four inputs and require 16 test vectors.For a 16 by 16 multiplier, 3836 test pat- terns are required.Actual experience indicates that production multipliers exhibit bridging faults that are not detected by testing the individual cells [7].
Bridging faults have been observed that affect ad- jacent (i.e., right-left or up-down) cell pairs.Ac- cordingly, they may be detected by exhaustively test- ing all overlapping one by two, two by one, or two by two subsets of the array.A 16 by 16 multiplier has N overlapping one cell by two cell subarrays, N2-2 overlapping two cell by one cell subarrays, and N2-N overlapping two cell by two cell subarrays.
Because one gate input is common across rows of cells and the second gate input is common across the columns, even the two by two subarrays of gated full adders have only nine inputs.If it is assumed for simplification that all of the N:-N overlapping two cell by two cell subarrays are comprised of gated full adders, a total of 114,688 test vectors are required.
In general the number of test vectors scales as O(N2), so this approach remains reasonable even for large values of N.
The overlapping segment testing may be .extendedto larger segments.For example, three cell by three cell could be used, but because the number of inputs to the nine cell subarray grows (it is 14 when all the cells are gated full adders) the number of test vectors grows quite rapidly.For the commercial multipliers, bridging faults that span beyond adjacent cells have not been observed, so the vastly increased test com- plexity to accommodate the three cell by three cell subarray does not seem to be warranted.
Six test options for a 16 by 16 multiplier are com- pared in Table I.In preparing this Table, each cell is assumed to have four inputs even though the cells along the top and left edge have fewer inputs.The one cell by one cell segment size requires only a couple of thousand test vectors, but cannot detect inter cell bridging faults.The one cell by two cell and two cell by one cell segment size require on the order of ten thousand test vectors each and will de- tect horizontal or vertical bridging faults between adjacent cells, respectively.The two cell by two cell segment size requires about a hundred thousand test *For all except the 16 by 16 case, the count of inputs and test vectors assume that all cells are gated full adders.
vectors and will detect bridging faults between ad- jacent cells (including diagonal bridging faults), with- out the much greater complexity of the three cell by three cell overlapping subarray or the full exhaustive tests.
Note that for many circuits, cell inputs and outputs are not easily accessible at the package pins.In such cases it may be necessary to add multiplexers (as shown in Figure 3 of McCluskey and Bozorgui-Nes- bat [17], for example) or scanning registers such as level-scan-sensitive design (LSSD) [20] so that the test inputs and outputs to subarrays can be easily set and observed, respectively.

CONCLUSIONS
This paper presents a test approach that is suitable for repetitive structures such as cellular arrays.As a result it applies to most arithmetic circuits.It is based on exhaustive testing of overlapping segments of the array and detects bridging faults in addition to stuck- at faults.The ability to detect arbitrary faults in- volving any cells within a designer selectable distance (i.e., the diameter of the segment) is unique to this testing approach.The universality and high coverage of the proposed technique make it attractive for test- ing current and future VLSI and WSI arrays.design, including high-speed computer arithmetic, systolic signal processor architecture, VLSI and WSI technology, and system prototyping.Previously at TRW, he managed the Independent Research and Development program for the TRW Defense Systems Group and the Digital Processing Laboratory in the TRW Electronic Systems Group.He developed the architectural and functional design of VLSI components which are in production; managed the development of the first semi custom integrated circuit with over 100,000 transistors; and managed high speed signal processor development projects including a 40 MSPS float- ing point FFT processor.Dr. Swartzlander is a member of the Board of Governors for the IEEE Computer Society, Editor-in-Chief of the IEEE Transac- tions on Computers, hardware area editor of A CM Computer Reviews, and founding Editor-in-Chief of the Journal of VLSI Signal Processing.He was an Editor of the IEEE Transactions on Parallel and Distributed Systems, and was an Associate Editor of the IEEE Journal of Solid-State Circuits.
Professor Swartzlander has written the book VLSI Signal Processing Systems (Kluwer, 1986) and edited five books including two collections of reprints on Computer Arithmetic (IEEE Com- puter Society Press, 1990).He has written or co-written over 100 papers in the fields of computer arithmetic, signal processing, and VLSI implementation.
FIGUREIllustration of Overlapping Segments of a Mesh.

FIGURE 3
FIGURE 3 Photomicrograph of Parallel Multiplier.