A Modified Approach to Test Plan Generation for Combinational Logic Blocks

Generation of test plans is a crucial step for testing VLSI circuits. This paper presents a modified approach to test plan generation for the BILBO test methodology. A few limitations of the existing approaches have been identified and methods to address these have been suggested. The proposed approach has been implemented for the general case of n-port combinational logic blocks (CLBs). However, due to limitations of space and for clarity, only 2-port CLBs are considered in this paper. For this case, the problem is modelled as a Step Scheduling Matrix and an algorithm is presented for the solution. The algorithm has been tested on a number of benchmark circuits and the results are compared with those obtained through existing methods. The effectiveness of the proposed approach is clear from the results, as it contributes to the reduction in total testing time as well as generates a larger number of test plans.


INTRODUCTION
With the increasing complexity of VLSI circuits, the tasks of gate-level fault modeling and test generation have become excessively time-consuming and expensive. To alleviate this problem, testable design methodologies (TDMs) are being increasingly adopted. One such TDM is the Built-In-Logic-Block-Observer (BILBO) technique, proposed by Koenemann et al [1]. The BILBO approach views a VLSI circuit as consisting of combinational logic blocks (CLBs), interspersed with interconnections and transporting elements like registers, buses, and multiplexers. Although, all of these elements need to be tested, this paper concentrates on testing the CLBs only.
In order to test a CLB, test patterns are applied to the input ports of the CLB and its output responses are collected and compacted. A set of registers serves as Pseudo Random Pattern Generators (PRPGs) and another set of registers serves as Multiple Input Signature Registers (MISRs). The test patterns propagate from PRPGs to the input ports of a CLB, and the output responses propagate from the output port(s) of the CLB to the MISRs. Such propagation takes place through paths consisting of registers, multiplexers, and buses. These paths merely transfer data and do not modify them in any way. Such paths are, therefore, called identity transfer paths or I-paths [2]. After  is generated for transferring test data to the input ports of a CLB and the CLB output responses to MISRs. The generation of a test plan consists of the following steps: i) Combination of the input 1-paths, ii) Combination of the output I-paths, and iii) Concatenation of the input and output I-paths. An I-path consists of a number of steps, where a step designates one clock cycle in which the test data propagates from one storage element to another.
Combination of I-paths for the different ports of a CLB essentially implies combining the steps of more than one path such that the combined steps can be executed concurrently. This is possible only if there is no resource conflict within the combined steps. A resource conflict occurs when two steps require the same circuit element simultaneously. If such conflicts exist between the steps to be combined, then these steps are skewed by inserting No-op steps in one of the I-paths in order to avoid the conflicts. A No-op step in an I-path holds the test pattern in a register, used in the previous step, for one clock cycle. For the input I-paths, it is required that the test vectors arrive simultaneously at all the input ports of a CLB. To achieve this, the task of I-path combination must not only generate a conflict-free combination of steps, but also equalize the lengths of the component I-paths. After the input and output I-paths have been combined individually, they are concatenated to generate the test plan. Although there are no intra-step conflicts remaining at this stage, the different steps of the test plan may still use common resources. Normally, this factor should not cause any problems since different steps are executed in different clock cycles.
However, in order to reduce the total test time, the test patterns are pipelined through a test plan. Due to this pipelining, two distinct steps sharing a common resource may overlap in the same clock cycle and thus result in a resource conflict. To alleviate this problem, the initiation of the consecutive iterations of test vectors through the pipeline is delayed by a suitable amount of time. This inter-iteration delay is called the initiation delay (D).
For a test requiring T iterations through a test plan of S steps, the total test time is given by S + (T 1)D [2]. Since T is usually large compared to S, the total test time is much more sensitive to D than to S. Hence, for the reduction of total test time, it is very important to minimize D. Abadir [2] has proposed an algorithm to combine n I-paths for a multiport CLB. In this algorithm, the number of No-ops inserted at every step has been minimized. Abadir and Breuer [3] have also considered the problem of pipelining the test vectors through a test plan, and have suggested a lower bound on D. An algorithm for minimizing D by inserting No-ops in the combined test plan has also been presented by them. Bhawmik [4] has formulated these tasks as a consistent labeling problem [5], and has solved it using a backtracking algorithm. However, in these approaches, the problems of I-path combination and D-minimization have been treated separately.
In this paper, we first show that the process of combination of I-paths can affect the lower bound on D. Accordingly, we propose an approach to I-path combination which refrains from increasing the lower bound on D, as far as possible. The earlier algorithms [2,4] carry out the task of I-path combination in the direction of test pattern propagation. However, as shown in the next section, this approach may sometimes inhibit obtaining a feasible combination even if it exists. In order to resolve this problem, our approach starts the I-path combination process from the port side of a CLB and proceeds outwards towards a PRPG or MISR. This approach always finds a feasible combination if it exists. To deal with some typical conflict situations, it may, however, be necessary to resort to backtracking to arrive at a feasible solution.
The following section presents the basis of our approach. It is followed by an algorithm for combining the I-paths for CLBs with two input/output ports. This special case has been modeled as a Step Scheduling Matrix and the heuristics employed in the twoport algorithm have been explained with respect to this model. The I-paths for n-port CLBs, where n -> 2, may be combined by repeated application of the two-port algorithm, However, this process of pairwise combination can render the value of D sensitive to the order TEST PLAN GENERATION 245 of selecting the pairs to be combined. Hence, to ensure a minimum D, all possible pairwise combinations may need to be tried. Since the value of n does not exceed 4 for most practical cases, this approach will not be too expensive from a practical viewpoint.
However, we do have a general n-port algorithm of which the 2-port algorithm is a specific case. The n-port algorithm is also based on heuristics that are similar to the 2-port case. However, due to space limitations, we are unable to present the details of the n-port algorithm.

BASIS OF THE PROPOSED APPROACH
Before presenting the basis of the proposed approach, we introduce certain notations which have been used in describing the 2-port algorithm.

Notations
Ik (1 <k <n): An Input I-path for port k of a CLB, where n number of input ports.
Ok (1 <k <n): An Output I-path for port k of a CLB, where n number of output ports.
Pk (1 <k <n): An I-path (may be input or output) for port k of a CLB. sk: number of steps in the I-path Pk. Ik (1 <k <sk): ith step of the input I-path Ik. Ok (1 <-k <-s): ith step of the output I-path Ok.
Pki: ith step of the I-path Pk. A test plan is generated by concatenating the combined input I-path and the combined output I-path.
Apart from the notation presented here, the I-paths are often represented graphically. In such representations, the individual steps are represented as nodes, and the conflicts by dotted edges. In the following paragraphs, we explain the basic strategies adopted in the proposed approach to test plan generation and their underlying rationale.

Approaching from the Port Side
The existing algorithms for test plan generation [2,4] attempt to combine the I-paths, starting from the test pattern generator side (for the input I-paths) and from the port side (for the output I-paths). But this approach may lead to the serious limitation of precluding feasible input I-path combinations even when they exist. Moreover, it is also prone to yield a higher value of D. These aspects are illustrated through examples.
Example 1: Consider the two input 1-paths to two ports of a CLB Fig. 2(a)). The nodes denote the steps Since the existing algorithms start the combination process from the input (pattern generator) side, 111 will be scheduled with 121, and 112 will be scheduled with 122 Since the test patterns must arrive at the CLB input ports simultaneously, the two input 1-paths must be synchronized in time (clock cycles). This is achieved by introducing two No-Op steps after step 122. The resulting schedule is shown in Fig. 2(b).
The No-Op step 122,, implies holding the contents of register R, resulting in a conflict between 11 and 122,. Since 122 is the last step in 12, this conflict cannot be resolved if the combination process starts from the pattern generator side and, hence, a feasible combination will not be attained.
Example 2: Consider two input I-paths as shown in Fig. 3(a). Note that these I-paths have no resource conflicts between them. Hence, when they are combined from the pattern generator side, we obtain the schedule shown in Fig. 3(b). In the combined schedule, Step 2 of the second 1-path (122) has to be followed by a number of No-Op steps, in order to equalize the two input I-paths. The 122 steps will hold up the resources used in the step 122 for three more clock cycles. This results in inter-step conflicts in the combined schedule. Specifically, the combined steps CI2 through CI 5 happen to share resources common to 122 ( Fig. 3(b)). If   (D) has to be at least 4 in order to avoid the inter-step conflicts. However, as will be shown shortly, the value of D could have been in this case. In order to address the problems highlighted by the preceding two examples, we start the I-path combination process from the CLB port side. Thus, the last steps of the I-paths are combined first--the preceding steps are combined subsequently. The advantage of this approach is illustrated through the same examples as shown in Fig. 2(a) and Fig. 2(b). For the two I-paths shown in Fig. 2(a), the combined schedule resulting from I-path combination, starting from the port side, is shown in Fig. 4 For the I-paths shown in Fig. 3(a), combination from the CLB port side results in the schedule shown in Fig. 4(b). Note that there is no interstep conflict in this combined schedule. Hence, the minimum value of D is in this case, as contrasted to the value 4 obtained by the existing methods [2,4]. The reason for starting the combination process from the CLB port side is based on the fact that the No-Op steps required for equalizing the paths are pushed towards the pattern generator side, instead of the port side.
Since there are no real steps preceding these No-Op steps, no additional resource conflicts can arise.
(previous) use the same register. Hence Dmi > n + 1. In the light of Theorem 1, our approach attempts to distribute the No-Op steps in the different I-paths and, thereby, minimizes the number of contiguous No-Ops in any 1-path as far as possible. Hence, the salient strategies adopted in our approach are: (i) Initiating the I-path combination process from the CLB port side. (ii) Attempting to minimize the number of contiguous No-Ops inserted in a particular I-path.
The following section explains how these strategies have been incorporated in our approach.

Minimizing Contiguous No-Ops
Abadir [2] attempted to resolve the resource conflicts (to obtain a feasible schedule) by minimizing the total number of No-Ops inserted at a particular frontier step. However, his approach does not exclude the possibility of two contiguous No-Ops being inserted in the same I-path. We observe that the number of contiguous No-Ops inserted in a particular I-path is a very important factor that affects the lower bound on D.

TWO-PORT ALGORITHM
For CLBs with two input/output ports, the problem of I-path combination can be conveniently depicted as a two-dimensional Step Scheduling Matrix. Since twoport CLBs are very common in digital circuits, this case is presented to highlight the main features of our approach. THEOREM 1: If n contiguous No-Op steps (involving register holds) are inserted in any particular I-path being combined, then the inter-iteration delay D of the combined test plan will be at least (n + 1) clock cycles.
Proof" Let s be a step of the combined 1-path such that the steps S i+l, s i+2 S i/n, all share a common resource (register). Now, let us assume that the minimum feasible D is Dmin < n + 1. Let Dmin p (1 <-p --< n). Therefore, during test pipelining, Step s of one iteration will be in the same pipeline phase as Step Si+p of the previous iteration. That is, Step si of the current iteration and Step Si+p of the previous iteration will be executed in the same clock cycle.
But, this cannot be allowed since s; (current) and Si+p 3.1.
Step Scheduling Matrix (SSM) Let P1 and P2 denote I-paths for two ports, and let m and n be the total number of steps in P1 and P2, respectively. Also, let n -> m, without any loss of generality.

The
Step Scheduling Matrix is a two-dimensional matrix of rn rows and n columns. Each element in the SSM is denoted by (i/), 1 -< _< m, and 1 -< j -< n, where and j denote distinct steps of P1 and P2, respectively. The rows and columns are numbered in such a manner that the lower rightmost comer of the SSM represents the steps that are nearest to the ports. Accordingly, for input I-path combination, the lower rightmost element is labeled (m,n), whereas for output I-path combination, it is labeled (1,1). 248 A. BASU et al.
If P1 and P2j share a common resource, then there exists a potential resource conflict between these steps. Such a conflict is shown as a cross (X) in position (i/) of the SSM. As an example, Fig. 5(a) illustrates two input I-paths of a CLB, with the corresponding SSM shown in Fig. 5(b). Fig. 5(c) illustrates two output I-paths of a CLB, and the corresponding SSM is shown in Fig. 5(d).
It may be noted that the placement of a cross (X) at any position (i) of the SSM implies that step of PI(P1i) cannot be scheduled with step j of P2(P2), since they share a common resource.

I-path Combination
In terms of the SSM, the task of combining the different steps of I-paths is depicted by placing markers, Application of these moves is now illustrated with an example. Fig. 6(a) shows two input 1-paths of a CLB. As before, the potential conflicts between the 1-paths are shown by dotted edges. Figure 6(  corresponding SSM. Note that crosses have been placed at the positions corresponding to the conflicting steps. As mentioned earlier, the process of I-path combination starts from the port side of a CLB. Accordingly, the task of placing markers in the SSM starts from the lower righthand corner. First, a marker is placed in position (5,6). Next, by a D-move, another marker is placed in position (4,5). Since both the D-move and H-move from (4,5) are inhibited by crosses, a V-move is made to place a marker in position (3,5). The next marker is placed at (2,4). Since both the D-move and V-move are inhibited at (2,4), an H-move is made to place the next marker at (2,3). The last marker is placed at (1,2) by a diagonal move. The resulting schedule is shown in Fig. 6(c).
It may be noted that the V-move applied at position (4,5) results in placing two markers in column 5. This implies that both the Steps 113 and I14 are scheduled with Step 125. This, in turn, implies that a No-Op has to be inserted after 125, so that I13 is scheduled with 125 and 114 is scheduled with 125,.
Similarly, the H-move at position (2,4) places two markers in the second row of the SSM. This implies that a No-Op has to be inserted after I12 so that 123 is scheduled with 112 and 12 4 is scheduled with 122.. These observations can be generalized as follows.
(1) Each vertical move in the SSM introduces a No-Op in the current step of the second 1-path.
(2) Each horizontal move in the SSM introduces a No-Op in the current step of the first I-path.
As shown in Fig. 6(c), the combined schedule of the 1-paths can be obtained by aligning the row and column indices of the marked positions in the SSM.
It may be further noted that 122 has been scheduled with Ill, and, consequently, I21 is scheduled alone. This may be viewed as delaying the first step of I1 by one clock cycle. However, since such delays precede the first step, it does not result in holding up any resources.
In the context of the preceding discussion, the process of I-path combination can be viewed as obtaining a continuous sequence of marked positions in the SSM. Such a sequence may be obtained using the following steps. The key step in this algorithm is the selection of the proper move. It is explained in the next subsection. 250 A. BASU et al.

Selecting a Move
As shown in Theorem 1, placement of contiguous No-Ops in a path adversely affects the lower bound on the inter-iteration delay D. Hence, the heuristics adopted for deciding on the moves in the SSM aim to avoid the placement of contiguous No-Ops in the same path, as far as possible. The heuristics are explained in the following paragraphs. As an example, consider the SSM shown in Fig. 7. Let the currently marked position be (5,6). No D-move is possible from this position. As shown earlier, a V-move or an H-move implies the insertion of a No-Op in either path. Moreover, with respect to position (5,6), the cross at position (3,5) is a VLC. Hence, even if a V-move is applied at position (5,6) marking the position (4,6), no D-move can still be applied from (4,6). This, in turn, implies that at least two contiguous No-Ops have to be placed in 12 if a  (4,4) is an HLC with respect to position (5,6), implying that at least two No-Ops have to be placed in I1 if an H-move is selected. It may be further noted from Fig. 7 that, for V-moves, the contiguous crosses at positions (4,5), (3,5) and (2,5) necessitate the insertion of three contiguous No-Ops in 12 for making a D-move possible. On the other hand, for H-moves, the contiguous crosses at positions (4,5) and (4,4) require insertion of two contiguous No-Ops in I1 before a D-move can be applied. Accordingly, the costs of an H-move or a V-move are defined as follows.
H-cost: If the presently marked position is (i,]) and if there are k contiguous crosses at positions (i 1, j p), p 1,2 k, then the H-cost (cost of a horizontal move from (i,])) is k. V-cost: If the presently marked position is (i,j) and if there are k contiguous crosses at positions (i 1), p 1, 2 k, then the V-cost (cost of a vertical move from (i,])) is k.
It is obvious that H-costs and V-costs signify the number of contiguous No-Ops placed in the first and second path, respectively. In this context, the rules for selecting the moves are outlined as follows. It may be noted that while computing the costs (HC)ij and (VC)ij, more than one level of lookahead for conflict is performed, and also that such computations are required only when both the H-move and V-move are the only possible candidates.

An Extension
The 1-path combination algorithm, as discussed in the previous section, fails to generate a solution if a bus or multiplexer is shared between the nearest-to-port steps of the two I-paths. Figure 8(a) shows part of a VLSI circuit, where there is a bus conflict between the last steps of input I-paths 11 and 12. Fig. 8(b) specifies the steps in each I-path, and the corresponding SSM is shown in Fig. 8(c). Since there is a conflict (X) in the lower rightmost position of the SSM, the algorithm, as presented, will not be able to initiate the combination process. In order to resolve this problem, the SSM is extended by an additional row, if there exists a conflict in the last step. This implies the addition of a new step 112., after Step 2 of I-path 11, as shown in Fig. 8(d). The two-port algorithm is then applied on this modified SSM. If position (2,1) in the SSM had a conflict, then a No-Op step 12 2, is added after Step 2 of I-path 12. This implies the addition of a new column to the SSM, instead of a row. The function of such No-Op steps is to hold the contents of the nearest-to-port register of the concerned I-path for one clock cycle, so that the conflicting steps are scheduled at different times. The combined input I-path, denoted CI, is shown in Fig. 8(e). Note that if the nearest-to-port steps had a register conflict, then the I-paths could not be combined at all since the same register has to latch or hold the data for two different ports at the same control step, which is impossible.

Backtracking
If, from a position (ij) in the SSM, none of the moves is applicable, then the algorithm resorts to backtracking. This is accomplished through the following steps. To illustrate the process of backtracking, consider the potential conflicts shown in Fig. 9(a). The corresponding SSM is shown in Fig. 9(b). After placing a marker at position (4,4) through a D-move, no further moves can be applied. Hence, the algorithm backtracks to position (5,5) and assumes a cross to be placed at position (4,4). Next, using lookahead heu-252 A. BASU et al. ristics, two vertical moves are selected to generate the schedule shown in Fig. 9(c).

DISCUSSION OF RESULTS
The two-port algorithm presented in the previous section has been applied to generate test plans for a number of VLSI circuits. A few CLBs from such cir-  Table II, that the values of D obtained by the proposed approach are less than those obtained by method A. Moreover, in some cases (Example 1), method A fails to arrive at a feasible combination, while method B succeeds in achieving a feasible schedule. In Example 3 of Table II, the proposed approach succeeds because of the facility of backtracking, whereas the existing approach fails to achieve a feasible combination. The 2-port algorithm has been generalized to the case of n-ports. However, due to space limitations, the extension is not presented here.

Further Results and Discussion
The proposed test plan generation scheme has been applied to a number of well-known synthesized data-   paths taken from the literature [6][7][8][9]. Table III   filter CLB #1 and in mcs6502 datapath). This is because of the fact that the proposed algorithm succeeds in certain cases where Method A fails. Even in the cases where the same number of test plans has been generated, the frequency distribution shows that the test plans generated by the proposed approach are clustered more in the lower values of D. This fact is evident from Fig. 11  has been presented to provide a quick reference about the relative performance of the two approaches as far as the the inter-iteration delay is concerned. The results clearly demonstrate the effectiveness of the proposed approach in yielding a lower value of D. Since the value of D is a very important criterion for determining the total test time, it is logically expected that the test plans generated by the proposed algorithm will help in reducing the total testing time.