Logic Synthesis for a Regular Layout

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits the device performance. Our experimental results are very good and show that symmetrization of reallife benchmark functions can be done efficiently.


INTRODUCTION
Performance improvement of ULSI ICs fabricated in deep sub-micron technology depends very strongly on the delay of interconnects. For the current leading technologies with active-device count reaching the tens of millions, the delay of interconnects is responsible for about 40-50% of the total delay associated with a circuit. With constantly improving technology and more metal layers being available for interconnections, this contribution is predicted to increase. As the amount of intercon-nects among devices has a tendency to grow superlinearly with the number of transistors, the chip area is often limited by the area needed to accommodate the interconnects. Therefore, the interconnect dimensions are scaled as much as possible along with the device and voltage scaling. So with the width and the thickness of the metal stripes decreasing and the average length of the interconnects, using current approaches to layout synthesis, remaining the same or increasing slightly, the resistance of interconnects increases. For delay calculation it is also necessary to consider the *Corresponding author. Tel.: 503 725 5415, Fax: 503 725 3807, e-mail: jeske@ee.pdx.edu tThis work was supported in part by the NSF grant MIP-9629419 and by the 1995 SIGDA/DAC Design Automation Award. 36 M. CHRZANOWSKA-JESKE et al. capacitance of interconnects. Luckily the capacitance per unit length usually does not change with scaling.
Therefore, it has become more and more important to be able to predict and control the length of interconnections. The obvious but quite challenging approach is to develop synthesis methods integrating logic and layout synthesis steps. Such integration could be accomplished by synthesizing functions with the objective being not a standard minimization of the number of gates or logic levels but generating a regular netlist with a defined interconnection structure. The regularity of the structure would permit the creation of a layout directly from the logic level description without any placement or routing, or alternatively a simplified placement and routing which would start from the "floor-plan" created with these regular structures.
The concept of a regular array to realize logic is an old one, but so far, only PLA-like structures have succeeded commercially. In 1972 Akers [1] proposed a universal, two-dimensional planar and regular array for arbitrary single-output functions. It was shown that any Boolean function can be mapped to such an array by the consecutive repetition of variables. But since the array size was calculated for worst case functions, such layout was very inefficient for real functions and the idea was not adopted. A multilevel, PLA-like array, called a Complex Maitra Logic Array (CMLA), was introduced in [8], but no efficient and effective algorithms to generate such representation have yet been developed.
In this paper we present a logic synthesis method for generating Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), a new, regular two-dimensional function representation for both completely and incompletely specified multi-output Boolean functions. PSBDDs can be directly mapped to a two-dimensional layout without placement and routing. The idea originates from an OBDD [2] representation for totally-symmetric functions and generalizes the known switch realizations of symmetric binary functions [7]. The meth-od is general and applicable to arbitrary multioutput incompletely specified Boolean functions, additionally the results can be improved when the original function is first decomposed to blocks realized as PSBDDs. We introduce synthesis methods for generating such regular representations and define the structure of an array to which PSBDDs can be mapped. A Join-Vertex operation, introduced in [9], is used to combine two geometrically-adjacent nodes such that the function is represented as a pseudo-symmetric network (twodimensional regular array with only local connections between abutting cells) instead of a binary tree or DAG. To further optimize PSBDD sizes, we define a flipped Shannon expansion in respect to a geometrical realization ofthe diagram. We define an array as a geometrical concept. Thus, for instance, PSBDDs can be mapped to a Shannon Lattice Array which is a two-dimensional array of multiplexers, each with two inputs and one output, connecting with four neighbors of a node, and one input (control variable) from a diagonal bus. PSBDDs, which have a structure of contact networks for symmetric functions, can also be implemented using pass transistors with inverters and buffers added. The remainder of this paper is structured as follows. Section 2 presents background on regular arrays. In Section 3 we describe Pseudo-Symmetric Binary Decision Diagram generation. The basic concept of function symmetrization is presented in Section 4. Newly developed heuristics for generating PSBDDs are described in Section 5. Comparison of PSBDD layouts to other function representations is given in Section 6. Section 7 presents our experimental results for the MCNC benchmark functions and Section 8 concludes the paper.

SYNTHESIS FOR REGULAR ARRAYS
The approach of Akers from 1972 was the only one in the literature that proposed an array which is similar to one of the possible implementations of LOGIC SYNTHESIS 37 PSBDDs. The array is based on a rectangular grid and uses multiplexer cells which are associated with Shannon expansions. The arrays of Akers are unnecessarily large, because the order and repetition pattern of input variables is universal and calculated once for all functions by repeating consecutively the same variables. The number of times each variable has to be repeated, in Akers' approach, depends only on the variable's position in the variable order. No efficient procedures for finding the order of (repeated) variables are given, and it is easy to show simple functions that have very large arrays.
Our approach is quite different from that of Akers. We do not want to design a universal array for all functions, instead we developed a layoutdriven logic synthesis method that gives efficient results for many real-life functions. We derived our ideas from the observation that a Binary Decision Diagram for a totally symmetric function is a regular two-dimensional structure. This is due to the fact that for totally symmetric functions every two geometrically-neighboring nodes on the same level of a planar drawing of a BDD are isomorphic and can be represented as one node. For nonsymmetric functions the geometrically-neighboring nodes are usually non-isomorphic and, therefore, the BDD structure is an (irregular) Directed Acyclic Graph (DAG) not suitable for mapping to a regular array. In our approach we first create a tree expansion, but after expanding each level, we combine together non-isomorphic geometricallyneighboring nodes on that level using the Join-Vertex operation, thus creating a layered regular Directed Acyclic Graph. During the Join-Vertex operation, variables are reintroduced back into the function, therefore, combining nodes leads in turn to the requirement of variable repetition. The regular diagrams created with the Join-Vertex operation are called Pseudo-Symmetric Binary Decision Diagrams (PSBDDs). In contrast to Akers approach, the variables in PSBDDs can be repeated in any order and the number of repetitions of a variable depends on a particular function rather then being precalculated universally. The concepts of node joining and non-consecutive variable repetition add much power to the diagrams. We propose a number of heuristics for variable ordering, and show that with a good order a substantial minimization of diagram sizes can be achieved. We use Shannon (S), and flipped Shannon (fS) expansions. Flipped Shannon expansion, very important for PSBDDs where the actual positions of nodes on the plane are considered, can be viewed as Shannon expansion performed for the inverted control variable. It obviously does not apply for BDDs where relations between nodes are not defined geometrically. In addition, we take advantage of "constant pseudo-expansions", which means we assume constant values in control variables. In our approach, which is feasible for multi-output, incompletely specified functions, arbitrary non-symmetric functions are symmetricized by repeating variables in order to realize them as regular arrays.
One possible way to implement PSBDDs is with an array of multiplexers, and we can represent it as a geometric concept in the following way. First let us define a general two-dimensional structure which we call Lattice Array. Lattice Array, shown in Figure 1, is the data structure that describes the regular geometry of a circuit. In this paper we consider a two-dimensional array of multiplexers each with two data inputs and one output, which can be connected to two other neighbors of a node, as well as one input (control variable) coming from a diagonal bus. Both polarities of variables are allowed for implementing Shannon and Flipped Shannon expansions. We say a variable has a positive polarity when it is present in a function, and has a negative polarity when a negation of the variable is present. Pseudoexpansions corresponding to constant values 0 and of control variables are also included.

DEFINITION 5 An Ordered Shannon Lattice Array
/s an ordered lattice array in which all cells are multiplexers.
Thus in an Ordered Shannon Lattice Array, on a diagonal, all cells are of type S, 0 or 1, or all cells are of type fS, 0 or 1. It can be proven that every binary function can be realized with such a structure, but in the worst-case an exponential number of levels is necessary (which means the control variables in diagonal buses will be repeated very many times). In the Akers's array the same variable is subsequently repeated without other variables interspersed and such arrays are called variable interval arrays. In our approach, however, we assume no constraints on variable order. In many cases this allows a dramatic decrease in the number of variable repetitions and thus in the size and delay of the design. We will focus our attention on the neighbor-to-neighbor connections, which in the case of four neighbors and four I/O connections constitute planar routing resources. The shape of implemented PSBDDs is approximately triangular or trapezoidal in various sizes.

GENERATING PSBDDs FOR COMPLETELY SPECIFIED FUNCTIONS
The idea of our approach originates from symmetric networks and BDDs. Let us recall two definitions of the symmetries which will be used here to explain our approach. If tWO variables exhibit non-equivalent symmetry, the function's two cofactors, fab' and fa'b, (in respect to these two variables) are equal and can be represented as one node in a planar drawing of the function's OBDD, as shown in Figure 2a. We assume that OBDDs are always drawn such that the true cofactor is drawn as the right child and the negative cofactor is drawn as the left child.
LOGIC SYNTHESIS Therefore, in order to take advantage of the equivalent symmetry we introduce a Flipped Shannon expansion which is shown in Figure 2b, where black nodes represent the equivalent nodes. If a Boolean function is totally symmetric with only non-equivalent symmetries holding between its variables, then its OBDD can be drawn as shown in Figure 3. The OBDD there has a desired struc-f= a'b'c' + a'bc + ab'c +ab FIGURE 3 An OBDD for a totally symmetric function.
ture, regular and with only neighbor-to-neighbor connections. Decomposition variables are assigned to diagonal busses. Such structures can be directly mapped to Ordered Shannon Lattice Arrays.
Unfortunately, not all functions are totally symmetric. The regular OBDD for a totally symmetric function is a result of merging together isomorphic geometrically-adjacent nodes. This merging idea is extended here by us for the case of non-isomorphic nodes through the Join-Vertex [9] operation presented below. The underlying idea of the Join-Vertex operation using the BDD and the PSBDD representations is shown in Figure 4. The penalty to be paid is the reintroduction of the expansion variables back into the function. The reintroduction of the variable makes it necessary to use the same expansion variable more than once which increases the number of levels.
Functionfcan be expressed using four cofactors of any two of its input variables as shown in Eq.
Generating a PSBDD using a Join-Vertex operation on nodes u4 and u5.
For the Eq. (2) to be satisfied, function g has to be equal to fa'b for a 0 and b 1, and to fab' for a= and b=0. So, if the two cofactors are not equal, to satisfy the Eq. (2), we use the Join-Vertex operation. The Join-Vertex operation given in Eq. (3) is defined for variable order (a, b}. on which more general lattices would be based. The concept of the Join-Vertex operation is very powerful and general in logic design as it applies to combining any two nodes which are not isomorphic (not necessarily combining neighbors), and therefore can find many other applications in decision diagrams and function representations.
We can verify the correctness of the Join-Vertex operation by substituting it back to Eq. (2).
Two elements of the Eq. (5), ab'bfa,b and atbb fab', are equal to 0 because the law of Boolean algebra states that btb 0. The resulting function is given in Eq. (6). f a'b %'b' + a'bfa, b + ab 'fab' + abfab (6) As can be seen, Eqs. (1) and (6) are the same, therefore, with the Join-Vertex operation the function remains unchanged. The law b b 0 of Boolean algebra or similar properties in nonbinary algebras must hold in any algebraic system 4

. THE BASIC CONCEPT OF FUNCTION SYMMETRIZATION
Applying the Join-Vertex operation to all geometrically-adjacent nodes on a level has the same effect as introducing a repeated variable in the process of function symmetrization using variable repetitions. The symmeterization of a function can be viewed in terms of introducing don't cares to the function. Let us discuss this in more detail. A repetition of a single variable introduces don't cares into the half of the Kmap minterms of a new function with the repeated variable, so the more variables are repeated, the more weakly specified the function becomes..If one starts from a completely specified function and repeats two variables, 75% of the minterms of the new function will be don't cares as shown in Figure 5. argument variables xr set to and other variables set to 0 (see Fig. 6). The layer of index S i, in an arbitrary function, is the set of cells of gma p that have exactly of its argument variables xr equal to 1. For an incomplete totally symmetric function F(Xl, x2,..., xr,..., x), for every Si, 1,..., n, all cells are either all l's and DC's or all O's and DC's [7].

THEOREM
Every Boolean function can be made totally symmetric (symmetricized) by repeating some of its variables [15].
The above theorem was presented for the first time by Arnold and Harrison [15] for a total of 2 variables for the n-variable function. These results were further improved by others and finally Lee and Hong [16] presented an iterative algorithm which optimizes the number of repeated variables based on partial symmetries. Below we present an illustrative reasoning of the symmetrization process. If for every value of the symmetry index the corresponding layer is consistent the function can be converted to a completely specified totally symmetric function by replacing all don't care cells in a layer of at least one "1" with 1-cells, don't care cells in a layer of at least one "0" with 0-cells, and a layer with all "-" with either all 0-cells or all 1-cells.
We say that variable x separates zero-cell zl from one-cell o in a Kmap when z c_ x and o c_ x or z c_ x and o c_ x. To simplify the discussion and the example given in Figure 6, we only consider non-equivalent symmetry. If for a given function there exists a layer with both ones and zeros (such as layer Sl(a,b) in Fig. 6a) by repeating a variable that separates these ones and zeros a new Kmap is created as shown in Figure 6b. In Figure 6a, both variables a and b are the separating variables for cell zl ab and cell ol ab so any of two can be used. In the new Kmap (Fig. 6b) the 0-cell and the 1-cell that were in the same layer in the previous map become now partitioned to two different layers. Because adding one variable partitions the set of cells to two sets, after a finite number of partitions there will be a single "1" or a single "0" plus don't cares in each layer (in the worst case).
Thus the process will always terminate (usually it terminates earlier without a need to have a single care cell in every layer).
In Figure 6b, just by repeating variable "a" all the layers become consistent. Figure 6c corresponds to a PSBDD for the function shown in Figure 6a and represents the totally symmetric function S '1'3 (a, a, b). DEFINITION 11 Symmetrization is the process of converting an arbitrary function to a totally symmetric function by repeating some of its variables. It creates a new incomplete function. DEFINITION  Observe that many functions characterized as non-symmetric are still lattice realizable.
A function can be totally symmetric, partially symmetric, pseudo-symmetric or non-symmetric. The type of the function can be found from the analysis of cofactors and their negations [5,6]. In the case of a PSBDD with two types of expansions, Shannon and flipped Shannon, we have two degrees of freedom for the algorithm; selection of S or fS for the level; and the order of variables (this takes into account repetitions, too). The selection of a good order of variables is based on generalized partial symmetries for cofactors.
DEFINITION 13 The generalized partial symmetries for cofactors are the following properties of cofactors and relations between pairs of (in general, multi-variable) cofactors.
(a) a single cofactor is an incomplete tautology with (fi 1). (b) a single cofactor is an incomplete tautology with 0 (f 0). (c) incomplete tautology of any two cofactors (fi =fj). (d) incomplete tautology of a cofactor with a negation of any another cofactor (fi fj').
Note that cofactors are calculated while creating a PSBDD and these symmetries can be applied to any cofactors of a (sub) function.
If the function is symmetric and complete, it is represented as a diagram with an arbitrary order ofvariables without any repetitions. If a function is partially symmetric or non-symmetric, a PSBDD is generated level-by-level, using different variable ordering heuristics until the entire function is mapped to a diagram with some variables repeated only if necessary. In the process of generating a diagram we need to try not only to decrease the number of variable repetitions, but also to decrease the total area occupied by the diagram.

Functions
The method to create PSBDDs can be easily extended to multi-output incompletely specified functions as illustrated in an example. First, in Figure 7 we give the overview of how the Join-Vertex operation can be used without modification for any multi-output function. A step-by-step illustration of the PSBDD generation is explained in Example and shown in Figure 8. The initial distances between root functions f, f2, and f3 as well as their orders can be arbitrary. The distance between two functions can be understand as the number of variables which are expanded in individual functions before the geometricallyadjacent nodes of two functions are joined together with the Join-Vertex operation. In Figure  7 the distances between all functions are equal to one (only variable a is expanded in the individual functions; all other variables are expanded after the functions are joined together). The distances and orders strongly affect the size of the solution layout and the delay value. Example 1 In Figure 8 functions f, f2, f3 are represented by three Kmaps. As shown in the figure, calculating the positive cofactorfa means replacing the half of Kmap corresponding to a with don't cares. Similarly, calculating the negative cofactor f, means replacing the half of Kmap corresponding to a with don't cares. In Figure 8a, the PSBDD generation process using Kmap is given and the Shared PSBDD is shown in Figure 8b. The Join-Vertex operation for the node is just the set-theoretical union of all care sets in its parent Kmaps.
The above example shows constructively that for every function we can design a PSBDD with repeated variables, thus every function can be symmetricized.

VARIABLE ORDERING HEURISTICS
The order of variables and the type of operation (S or fS) influences very strongly the size and shape of a PSBDD. As these diagrams are related to OBDDs, our first approach was to examine variable ordering methods used for BDDs. A number of successful variable ordering heuristics for OBDDs [13]  fla' w v f3a W afl dp a'f2a, V af2 + a'fa, positions of two consecutive variables requires Therefore, these methods cannot be adopted for the recalculation of the OBDD's vertices for only PSBDDs. The variable order has to be determinone level, while in PSBDDs such operation would ed before or during PSBDD generation. We use require the recalculation of vertices in all levels function characteristics to determine the order of following the levels of the exchanged variables, variables. LOGIC SYNTHESIS 45 In this section we first focus on developing heuristics to generate PSBDDs without using any symmetry information. As it will be shown, such heuristics can be developed independently and then combined with symmetry information to improve results. We compare the orders of variables generated by our heuristic algorithms with the symmetry properties of the tested functions to evaluate our approaches. In most tested benchmark functions the symmetric variables are placed together at the beginning of the variable orders, which is the best strategy for minimizing the sizes of PSBDDs. Some characteristics of the function variables which are used in our methods are given below. DEFINITION 14 A variable appearance is the number of cubes in an optimized two-level function representation in which a variable is present. DEFINITION 16 A negative appearance is the number of cubes in an optimized two-level function representation in which a variable is present in negative polarity.
Initially we created an algorithm called "Fixed Order Method" in which the order of expansion variables was determined at the beginning of the PSBDD generation process based on variable appearances in the root function. For incompletely specified functions, the variable appearance is calculated using only "ON" (true) terms. All original function variables were used as expansion variables in the determined order, and the set of corresponding decomposition levels is called the first loop. Next, the variables which were reintroduced to the function by the Join-Vertex operations were used again as expansion variables in the same order as in the first loop and created the second loop. This procedure continues until a function is completely decomposed.
In Figure 9, three PSBDDs for the non-symmetric function f for variable orders {c, a, d, b}, {b, c, a, d } and {c, b, a, d} are presented. Variable loops are indicated. Please notice that the variable order in all loops is the same, however, some variables may be missing in higher loops. No Join-Vertex operation was necessary for the diagram in Figure 9c, therefore no repeated variables appear in the expansion.
The influence of the variable order on the size of PSBDDs can be observed. The number of the expansion nodes is nine for the cadb order and cbad order, and eighteen for the bcad order. Vertices which are marked with "." were created using the Join-Vertex operation. Please notice that in Figure 9b variables a and d appear twice in the path and variable c appears .three times. A number of PSBDDs for different functions from the MCNC benchmark set were generated using Fixed Order algorithm, but their sizes were quite large.
Our first improvement was to allow different orders of variables in different loops. Variable orders for each loop were defined based on variable appearances in the function representation at the beginning of each loop. The justification behind this heuristic is that a variable with higher appearance reduces a larger number of cubes/ terms when cofactors are calculated. Such an algorithm was implemented and we noticed small improvements for some benchmark functions.
In our next approach we decided to relax loop restrictions and all variables appearing in the function were used in the selection of the next variable. Two groups of methods were developed; Greedy and Look-ahead.

S.1. Greedy Methods
We dynamically choose a variable for the next level expansion by recalculating appearances of all variables at each decomposition level. The variable with the maximum appearance number is chosen. Two ways of breaking ties were implemented. G1-choose a variable with the minimum difference between positive and negative appearances. G2-choose a variable with the maximum difference between positive and negative appearances.

Look-ahead Methods
To choose the expansion variable for the next level, the expansion to the next level is performed for all variables and both expansions, Shannon and Flipped Shannon. We use only one type of expansion per level. All adjacent isomorphic nodes are detected and combined together, and the number of nodes and literals for each expansion variable is calculated and used in the next-level variable selection. Comparing to the Greedymethods the complexity of Look-ahead methods increases approximately 2n times.
L1. a variable which generates the minimum number of nodes in the next level is selected.
In case of a tie, the variable which has the minimum appearance is selected. L2. a variable with the minimum appearance number is selected. In case of a tie, the variable which generates the maximum number of nodes in the next level is selected. L3. a variable with the minimum appearance number is selected. In case of a tie, the variable which generates the minimum number of nodes in the next level is selected.
The diagram presenting all methods is shown in Figure 10. There is a common-sense justification behind each of these heuristics. For the given order of variables and every variable using one of two  being pursued. In this paper, we present a simplified analysis and comparison between two representations, a PSBDD and a BDD, and between their mappings to a two-dimensional array, built with neighbor-to-neighbor connected multiplexer cells and diagonal busses. For illustration we use the function given in Eq. (7).
f atbrcre + acrde + acde + acdre + a'e'd'e' + a'c'de (7) The diagram and its implementation, for the function from Eq. (7), realized as a BDD and as a PSBDD are given in Figures 12 and 13, respectively. It can be observed that the overall BDD layout is larger than the PSBDD layout and not as regular. In addition, the BDD representation requires more diagonal buses (8 versus 7 for the PSBDD) and has two variables assigned to the same bus for two diagonals (e with a, and d with c), which results in additional connections. Obviously, creating a layout using a BDD representation is more complicated than using a PSBDD representation. Based on the above example we expect that there exist functions for which the LOGIC SYNTHESIS 49 PSBDD layout is more compact and delay is shorter than the BDD realization, however more detailed comparison is needed to determine the quantitative relations. The comparison between the number of nodes and levels in BDDs and PSBDDs for the MCNC benchmark functions are given in Table II. PSBDDs are regular structures, therefore, it seems natural to compare them with PLAs, the regular two-level representation which is still used in design implementations. For totally symmetric functions, it is easy to find examples when PSBDD layout is better than PLA layout, because there are no repeated variables. For instance assume the function given below.
S2'3(a,b,c,d) abe + ac'd + bc'd + a'cd + b cd + bcd + acd (8) The diagram and its implementation, for the function from Eq. (8), realized as a PLA and as a PSBDD, are given in Figures 14 and 15, respectively. When realized as a PLA (Fig. 14a) it has 14 AND gates and 6 OR gates, therefore, the area cost of its realization can be estimated as 20 gates.
For comparison we implement the same function, from Eq. (8), using the PSBDD shown in Figure 15a. It requires 6 mux cells and 3 gate delays when implemented in the Ordered Shannon Lattice Array, as shown in Figure 15c. The multiplexer array is built with abutted multiplexer cells, and a unit multiplexer cell is shown in Figure 15b. Assuming the cost of a mux cell to be equal to that of two AND gates and one OR gate and the delay of that cell to be equal to two gate delays, the total cost of the PSBDD realization is 18 gates and 6 gate delays without wire delays. Therefore, we LOGIC SYNTHESIS 51 f abc' + ac'd + bc'd + a'cd + b'cd + bcd' +acd' can observe, that for the given totally symmetric function, the PSBDD layout is superior both to the PLA and the PLA with the OR plane realized as a tree.
Now, we will generalize our observations by analyzing the PLA and PSBDD layouts for a symmetric function on n variables. Because the PSBDD representation is developed primarily for deep-submicron technologies, we assume that wire unit delay is equal to gate delay. The total number of cells (muxes) needed to realize an arbitrary (thus including the worst case) symmetric function of n variables as a PSBDD is n2/2 and the area is equal to 2n 2 gate area (the area of the multiplexer is equal to the area of 4 gates). The delay is equal to the number of levels, which is n, multiplied by two (two gate delays per level). For an arbitrary symmetric function realized as a PLA, the total number of columns is k (k is a number of terms in SOP) and the total number of rows is 2n. Thus, assuming wire delay equal to gate delay, the delay in PLAs is 2n + k unit delays. The ratio given in Eq. (9) shows that for totally symmetric functions a PSBDD implementation has smaller delay than a PLA implementation. And from the area comparison in Eq. (10) we conclude that the area of the PSBDD layout is smaller for symmetric functions with k larger than n. It should be noted that for this comparison we have chosen the multiplexer implementation of PSBDDs, which is the least favorable.
delay PLA 2n + k =>1 fork>0 (9) delay PSBDD 2n area PLA area PSBDD (2n + 1)k 2n 2 > for k > n (10) Using the same delay and area assumptions and the same evaluation procedure as above, we compare areas and delays for a number of benchmark functions implemented as PLAs and as PSBDDs, and we present results in Table II. For PSBDD calculations we substitute the number of function variables, n, with the number of levels in a PSBDD, 1. (1_> n).

EXPERIMENTAL RESULTS
The algorithms are coded in the C language, and run in the UNIX environment on SPARC workstations. In Table I the results for functions from the MCNC benchmark set are presented. The function name, the number of input variables, the output number, and the number of terms in the Sum-Of-Product (SOP) representation, optimized with Expresso, are all given in columns one, two, three and four, respectively. In the next three columns the results for Fixed-Order Method are given; the number of loops (#1o), the number of levels (#1e) and the number of nodes (#no). The results, the number of levels and the number of nodes, for Greedy Methods, G1 and G2, are given in the next four columns. In the next six columns, the results for three Look-Ahead Methods, L1, L2, and L3 are listed. The "-" means that the PSBDDs could not be generated using the particular algorithm with the given memory and time limitations.
It can be noted that for most of the tested functions the Look-ahead heuristics, especially L3, give better results than the Greedy ones. However for some functions, as for example cm162a and count, the results were best for L1 heuristic. In a few cases, example 2 (output 58), and sao 2 (all tested outputs) the Fixed-Order Method gives the better results than the other methods. Reported results were generated on relatively medium sied functions to allow us to better understand and analyze these algorithms for future research. In addition, there exist functional decomposition methods which can be used as preprocessing, therefore the size of the function is not of great concern at this time.
It can be easily seen that for these real-life functions we have generated PSBDDs with acceptable numbers of nodes and levels. For the majority of the tested functions the number of levels is smaller than two times the number of function variables. Only for function clip (both outputs) it is close to three. This function is currently being analyzed to give us hints for further improvements.
In Table II we compare PSBDDs with Reduced Ordered Binary Decision Diagrams (ROBDDs) generated by the algorithm from [3] and OBDDs generated with the algorithm from [5]. Column meanings are the same as in Table I. As was shown in Section 6, mapping OBDDs to a two-dimensional array is not a direct process. It usually requires adding dummy nodes to make routing feasible. Therefore, the final area and delay could be larger than suggested by the number of nodes and the number of variables. In case of ROBDDs, which are not planar, it is necessary to duplicate nodes to make ROBDDs planar and add dummy nodes for routing. Therefore, the initial conclusion can be drawn that, despite the larger number of nodes, PSBDDs are attractive alternatives and should be further investigated. In the same table we also included comparison with PLA for some benchmark functions. Both delay and area for PSBDDs and PLAs are calculated using Eqs. (9) and (10). However, for PSBDD calculations for non-symmetric function in the place of n, the number of function variables, we use the number of levels in PSBDD l, which is always larger or equal to n. As it can be observed, for a number of benchmark functions delays were smaller for PSBDD implementations. The area was also smaller for functions where the number of SOP terms is larger than a number of function variables. We expect the delay and area of PSBDDs to decrease with further improvements in PSBDD generation algorithms.
One must also remember that, to show the power of this approach, only non-decomposed benchmark functions were tested and no symmetry information was explicitly used in the present experiment. To understand better how our heuristics work we compared the variable orders generated by our heuristics with the functions' symmetry sets, as shown in Table III for L3 heuristic. The number of levels and the number of nodes in PSBDDs are given in columns labeled "#1e" and "#no", respectively. It is indicated by "y" in column "match" if variables from a symmetry set are together in the variable order and "y" in column "on top" indicates that the symmetry set was placed at the beginning of the variable order. Upper case letters indicate complemented variables. For all but one of the reported functions we found a match and the symmetry set was placed on top of the order, which indicates that our heuristics are really good and generate good orders of variables. Interestingly, for a high percentage of functions that LOGIC SYNTHESIS 53  would be characterized as non-symmetric in previous papers [3], we still find isomorphic nodes and realize these functions in lattices without repeated variables. The generated results are good in terms of the small number of variable repetitions and the small number of nodes. The small number of repetitions is due to the following reasons: (1) there are many partial symmetries in these functions [11], and our heuristics take those symmetries into account (2) it was shown experimentally that many real-life functions have a lot of single variable symmetries [11], (3) even if there are initially no symmetric variables in a function, they can be created by repeating variables and applying the Join-Vertex operations.
Power analysis of the presented approach will not be discussed here, however it should be mentioned that the power dissipation associated with interconnects can be easily determined because in our approach the interconnect length and delays are known directly from the diagrams. That also allows to accurately estimate various circuit/ layout parameters before the actual layout is completed. Using these algorithms we have demonstrated that a regular multilevel, two-dimensional representation of a function can lead to practical solutions.

CONCLUSIONS
Our experimental results demonstrate that effective heuristics can be developed to minimize the size of PSBBDs by proper variable ordering and very good results can be obtained for practical benchmark functions. Next, we showed that by adding one more expansion type, flipped Shannon, in Look-ahead methods, the numbers of nodes and levels were smaller when compared to pure Shannon PSBDDs. Dynamic generation of the variable order proved to be a good approach in situations where variable exchange-based methods are totally unpractical. At a time when interconnection delay is becoming the major factor in limiting device performance, these diagrams, which offer localized connections and well-defined structure, are one of the solutions to the problem.
Our method is good for completely as well as incompletely specified functions. It can be generalized by allowing more powerful neighborhood geometries (more inputs and outputs from neighbors while maintaining a regular structure) and by mixing control variables in levels, which is an extension to Free Pseudo-Symmetric Diagrams. This concept can also be extended to function representations based on XOR gates as was shown in [10].
In conclusion, there are important advantages to PSBDDs from the point of view of deep submicron technologies, because: (1)connections are short and based only on local cells abutting, (2) delays are equal and predictable, (3) late-arriving variables can be placed closer to the output, (4) logic synthesis can be combined with layout, so that no special stage of placement and routing is necessary or it can be a good starting point for specialized physical design algorithms, and (5) power estimation is simplified as the interconnect contribution can be easily calculated from the length of interconnections. Our Look-ahead methods of variable ordering for PSBDD generation offer significant improvements in reducing sizes and delays of PSBDDs.