Delay Time Estimation Model for Large Digital CMOS Circuits

Delay time estimation in simulation or design verification step during a design cycle 
has become more and more important as the meaning of performance prediction. This 
paper proposed a delay estimation model for digital CMOS circuits, which works 
in gate-level but the modeling process includes the characteristics of MOSFETs. This 
model can handle the variation according to the kind of gates, input transition time, 
output load(fan-out), and transistor sizes of a gate. The procedure to find the general 
model was that, a delay model for CMOS inverter was extracted first, then it was 
extended to other gate by converting it into an equivalent inverter. The resulting model 
was evaluated and compared with SPICE simulation, which showed that the proposed 
model has the accuracy of less than 5% relative error rate to the SPICE results for each 
case and the speed of about 70 times faster than SPICE.


I. INTRODUCTION
Increase in integration ratio has influenced to many areas in design, fabrication, and test. Among them, design verification and performance estimation are the most important steps [1]. Especially for delay time estimation, the previous method in gate-level (each gate is pre-simulated in circuitlevel to find the gate delay, which is used to find the total delay in a gate circuit by adding all the gate delays in the critical path [2]) is not sufficiently accurate any more. Meanwhile a circuitlevel simulation can be used for delay estimation, but consumes the cost and time very much [3,4].
A special method to find delay time of a given logic gate or circuit has been demanded since 1960's and lots of researches have been performed from the one in [5], although it [3,4] because it has been dominating other technologies. The principal gate of those methods was the inverter because the structure of a general CMOS gate can be thought as an extension of a CMOS inverter [3,4,6,7]. Researches to find a method calculating delay time easily have been categorized into two groups: look-up table methods [8,9] and delay time calculation methods [10][11][12][13][14][15][16][17]. A table look-up method has a trade-off between the cost in establishing the table and the accuracy. Also, they don't have enough flexibility for various factors affecting delay time, such as input transition time, fan-out, output capacitance, sizes of MOSFETs, etc. The calculation methods are to construct a special delay model and can be divided into two groups: with [10-13] and without [14,15] the properties of the circuits or MOSFETs. The latter methods considered many factors affecting the delay time but they are not enough for more general cases where the sizes of MOSFETEs, output capacitances, etc., are varied. In remodeling methods, RC model could be used for a MOSFET [10] but it could not model exactly enough to include the nonlinear property of MOSFET with linear resistor. In 1990 and 1991, delay models for inverter and other logic gates were modeled with c-power MOSFET model [11,12], but they considered only the case of very small input transition time, resulting in the decreasing tendency in accuracy as the input transition time increases. This drawback was resolved in [14] by including many presimulation steps.
Recently in [15], similar to [l l, 12] but more precise model has been published, which considered the velocity saturation effects and the gate capacitances of MOSFETs. The error rate to SPICE of this model was with 8%. Also in [16], output load was modeled with an RC model and differential equations were solved. This paper insisted within 3.5% of error rate to SPICE without mentioning the calculation speed. This paper proposes a model for CMOS logic circuits, which can predict the delay time of a given circuit with the accuracy competing the SPICE circuit-level simulation and the speed not much slower than gate-level simulation. This model can handle the variation in transition time of input signal, output capacitance, fan-out, and sizes of MOSFETs. As the procedure to construct a general delay model, an inverter model is first constructed, and then it is extended to other gates by converting them into the equivalent inverters. The resulting model is compared with the SPICE simulation for inverter, NAND, and NOR gates in various situations, to show that the proposed model is very efficient in accuracy and speed.

II. REMODELING MOSFET AND INPUT SIGNAL
First, we remodel the characteristics of MOSFET and input signal to simplify the modeling process.  As shown in Figure 1, this paper assumes that the boundary voltages between saturation and linear regions are the same for all VGS. This is to include the characteristic effect [18][19][20][21] when the transistor size becomes smaller by scaling down and is modeled from the empirical data that the boundary voltages have tendency to move to the origin as decreasing the dimension of MOSFETs.

II.2. Input Signals
In general, a signal in a circuit can be thought as an output of the previous gate and it looks as the shallow-lined in Figure (7) where /cap is the current to Cr. In real operation, /cap is not simply the saturation current and should include the current through the resistors of the models in Figure 3. This is known as leakage current and is the reason why the previous works showed inaccurate results in large or small input transition time. In this paper, the operation of an inverter in Figure 3 is divided into six phases to handle the leakage current properly. This division was performed by figuring which operational phase the leakage current is dominant in. The resulting operational phases are specified in Table I, which is for the case of falling input. For the case of rising input, similar phases can be obtained and they are omitted here. In the table, the representative notation (Vml Vm6) is the output voltage in the corresponding operational phase. For example, the output voltage satisfying the conditions of Vo < Vsn and 0 < _< tinv (which is equivalent to Vinv_< Vin < Vm)) is expressed as Vml. In this phase, nMOSFET is in linear region and pMOSFET is saturated. Therefore, the model of Figure 3(c) can be used, resulting in ff -+-/ tiny + / ,.)/e(tinv-IVthpl/Tf)/Rt, snCt, For Vm2 nMOSFET must be in linear region. But in this paper, the leakage current in this phase is neglected that it is expressed as Rn-oc. For Vm5,  are not included for a very fast input.

III.3. Delay and Transition Time Calculation
With the six phases in Table I, for rising output. For falling output, tf should be replaced with tr.

IV. EXTENSION TO OTHER GATES
For other CMOS gates than inverter, this paper constructs the models by extending the inverter model such that the parallelly or serially connected MOSFETs are combined into one equivalent MOSFET resulting in the equivalent inverters. In this process the problem occurs when serially G Gao + (U-1)Gas While, the parallelly connected N MOSFETs are easily modeled by multiplying the drain current by N or reducing the resistance by the factor of 1IN. It also affects the delay time how many inputs are devoted to drive the gate and which inputs devote to change the output, but the model resulting from the above process has been empirically turned out to handle it quite accurately. Thus, this paper does not include further processing for it.

V. COMPARISON WITH SIMULATION RESULTS
The model proposed above was implemented with C-language and the calculation results were compared with SPICE simulation. The MOS-FETs' dimensions used are shown in Table II. SPICE simulation was performed with empirical model(MOS 3).
First, a single stage inverter is compared by varying the input transition time and the output load(fan-out, fo), which is shown in Figure 4 for output rising and falling cases. In the figure, both the absolute delay values from the model and simulation are shown and the relative error rates of the results by the proposed model to the SPICE results are accompanied. In the figure, fo means the fanout factor such that fo=2 means that the output drives two CMOS inverters. As in the figures, the proposed model has the ability to predict the delay time with error rate less than 5% to the SPICE simulation for both the rising and falling cases. Figure 5 show the comparison results for NAND and NOR gate similiarly to Figure 4, in which the extended model to the NAND or NOR type gate also has the accuracy within 5% of the relative error rate to SPICE. In Figure 5, only the output rising cases are shown, but the falling case would show the similar values.
For the general cases of cascading and signal inputting, the 16 gates are cascaded as Figure 6 for inverter, NAND, or NOR gate. The comparison results for each gate are shown in Figure  7, which also show that the relative error rates are still within 5% to SPICE, regardless of the type of the gate and number of cascaded stages.
As in the figure, the relative error rates become smaller as the number of stages increase, by which it can be said that the model proposed is more accurate as the cascaded stages increases. That means, this model is more appropriate to a large circuit. For more general situation of a gate circuit, 16 stages are cascaded as in Figure 8, where the type of the gate and the output load capacitance in each stage are randomly selected. The load capacitance is between 0.05[pF] and 0.5[pF] representing the arbitrary load capacitance and/or fanout. The comparison results for this circuit are shown in Figure 9 and it also show that the proposed model is accurate enough that the relative error rate to SPICE is less than 5% for the arbitrary output capacitance and the type of gate as well as the arbitrary input transition time. Also, in the case that two or more gates are cascaded, the error rate is within 2% that the proposed *falling *rising fo=6 SPICE we---fo=6 SPICE 1.6 --*--fo=6 MODEL fo=6 MODEL --,m fo=2 SPICE 1.4 ,r--fo=2 MODEL  model is more appropriate to the case of cascading several gates than the case of single gate.
In circuit design, the width and length of a MOSFET need to be adjusted for various reasons. Thus, the ability for the proposed model to predict the delay time in a CMOS circuit for the various relative sizes of MOSFETs is examined. As the method, the width and the length of nMOS are fixed(W 2 lam, L 0.8 lam), while the width( from 1.01am to 61am) or the length(from 0.61am to 3.01am) of pMOS is changed. The increasing step is 0.5 lam and 0.2 lm for the width and the length, respectively. The results are shown in Figure  F l " s t a g e G15 ste G,14 1 1 3 s t a g e [ G13 l i 2 s t a g e are shown in Figure 11. It can be said by the figure that the proposed model can estimate the delay time of given circuit more than 70 times faster than the SPICE simulation. This speed is not much slower than the gate-level timing calculation.

VI. CONCLUSION
In this paper, a model to calculate delay time for CMOS logic circuits proposed. This model can handle all kinds of CMOS logic gates by converting an arbitrary gate into an equivalent CMOS inverter. It is purely calculational model and need almost no pre-simulation step. The methodology for the proposed model to calculate the delay time of a given circuit is to calculate the output voltages for the appropriate operational phases, relate them to the time, and calculate the delay time.
The proposed model can calculate the delay time regardless of the input transition time, output load(fan-out number), or the sizes of MOSFETs. From the results by comparing the calculated results from the proposed model to those from the SPICE simulation, the proposed model has the accuracy competing the SPICE results such that the relative error rate to SPICE is within 5% and Consequently, the delay model proposed here can be used in the simulation step during the design cycle to predict the delay of a CMOS logic circuit without losing the accuracy of circuitlevel simulation and with the speed high enough. This model is especially useful to predict the operational frequency for a large CMOS logic circuit which is usually calculated with the critical path [2] in a given circuit.