Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis*

Pseudorandom testing has been widely used in built-in self-testing of VLSI circuits. Although the defect level estimation for pseudorandom testing has been performed using sequential statical analysis, no closed form can be accomplished as complex combinatorial enumerations are involved. In this work, a Markov model is employed to describe the pseudorandom test behaviors. For the first time, a closed form of the defect level equation is derived by solving the differential equation extracted from the Markov model. The defect level equation clearly describes the relationships among defect level, fabrication yield, the number of all input combinations, circuit detectability (in terms of the worst single stuck-at fault), and pseudorandom test length. The Markov model is then extended to consider all single stuck-at faults, instead of only the worst single stuck-at fault. Results demonstrate that the defect level analysis for pseudorandom testing by only dealing with the worst single stuck-at fault is not adequate (In fact, the worst single stuck-at fault analysis is just a special case). A closed form of the defect level equation is successfully derived to incorporate all single stuck-at faults into consideration. Although our discussions are primarily based on the single struck-at fault model, it is not difficult to extend the results to other fault types.


INTRODUCTION
Defect level (DL) is an important indicator of test quality, and is defined as the percentage of a product, such as a chip, that is defective and is shipped for use after test. Thus, high DL in a product is not acceptable, especially, for the design of highly reliable systems. Low DL can be achieved by either increasing the fabrication yield or enhancing the defect coverage of circuit testing. However, VLSI manufacturing is subject to process contaminations which makes perfect yield impossible. Ideally, testing should be performed to detect all chips that contain defects. But, there are too many different defect types as the fabrication density of VLSI circuits keeps increasing. Instead of trying to detect all defects, testing process is designed to achieve a tolerable DL under constraints such as test application time, test generation time, and test storage. Built-In Self-Testing (BIST) has been one of the most promising alternatives to achieve high test quality using limited test resources [1,2]. The main idea of BIST is to have the chip test itself. Pseudorandom self-testing is a very popular BIST technique [3,4], which has been successfully applied to many commercial products [5,6]. Pseudorandom testing deals with testing a circuit with test patterns that have many characteristics of random patterns, but the entire test sequence is generated deterministically using built-in digital devices such as linear feedback shift registers (LFSRs) [2,4,7]. Thus, the entire test sequence can be regenerated by giving the same state or seed value. Pseudorandom patterns can be generated with or without test vector repetitions depending on the test length and the circuit structure of test pattern generators. If the circuit under test (CUT) is a combinational circuit and the faults do not induce any sequential behavior, then pseudorandom patterns without test pattern repetition are preferred to increase the fault detection probabilities. In this work, we assume that the CUT is a combinational circuit or a sequential circuit with full scan design, and faults occurring will not induce any sequential behavior. Thus, the DL analysis using pseudorandom test patterns without test vector repetition will be investigated. The DL estimation for pseudorandom testing has been thoroughly studied in [8] using the technique of sequential statistical analysis [9]. Many important DL properties under pseudorandom testing have been identified; unfortunately, no closed form can be derived to well describe the relationships among DL, pseudorandom test length, fabrication yield, the number of all possible test patterns, and the CUT testability. The difficulty of deriving a closed form for the DL equation lies in the involvement of very complex combinatorial enumerations. Thus, deriving the DL ofpseudorandom testing relies on computer enumeration which is not only time-consuming but also inaccurate (because of intolerable numerical errors accumulated during the enumeration process). Additionally, the previous analysis in [8] is mainly based on the worst fault analysis which is not adequate as far as high test quality is concerned.
In this paper, the DL analysis for pseudorandom testing is considered from a different viewpoint which successfully avoids the tedious computer enumeration process. First, a Markov model [9] is proposed to describe the pseudorandom test behavior and a simple differential equation is extracted from this model. A closed form for the DL equation can then be derived by solving the differential equation. Of course, the differential equation extracted does not faithfully reflect the real situation since pseudorandom test patterns are discrete. However, the test patterns are virtually continuous as more and more test vectors are applied (generally, on the order of several millions). Our results demonstrate that the approximation is very accurate and computationally cost-effective. The deviation induced by the differential approximation is almost negligible, when the number of pseudorandom test patterns is large.
Most investigations to the DL analysis of pseudorandom testing are mainly using the worst or average single stuck-at fault detectability, and this is inadequate as far as high test quality is concerned [10]. To solve this problem, the proposed Markov model is extended to incorporate all single stuck-at faults into consideration. A closed form is also obtained to illustrate the relationships among DL, pseudorandom test length, fabrication yield, the number of all possible test patterns, the CUT testability, and the number of single stuck-at faults significantly contributing to DL. Results show that the worst single stuck-at fault analysis is just a special case of the all single stuck-at fault analysis. The deviation can be very significant when the number of low-detectability faults is large. In fact, analysing the DL of pseudorandom testing by considering all low-detectability faults which are weighted by the probabilities of their occurrence can dramatically enhance the test quality. Although the discussions mainly focus on single stuck-at faults, the results can be easily extended to other fault types as long as their corresponding detectabilities can be derived. This paper is organized as follows. Section 2 gives the required background on DL analysis, and Section 3 presents the Markov model and the DL analysis for pseudorandom testing based on the worst single stuck-at fault assumption. Results are then extended to consider all single stuck-at faults in Section 4. Section 5 discusses the impacts of fault model, fault occurrence, fault distribution, and fault coverage distribution to the DL analysis.
Concluding remarks are given in Section 6.

BACKGROUND
The DL of circuit testing is the probability of shipping defective products, and its value should be controlled to be as small as possible. If the number of defective products shipped for use among the total number of products shipped is known, then the DL can be estimated using the following equation Number of defective products shipped 1)r Total number of products shipped In [11], the DL of circuit testing is determined as a function of fault coverage (the fraction of faults detected) and yield based on the following assumptions: (1) The chip has exactly n faults and m of them are tested; (2) The probability of a fault occurring is independent of whether any other fault has occurred or not; and (3) Each fault has an equal probability of occurring.
The assumptions ensure the uniform distribution of faults. Equation (2) shown below is derived using probability theory DL-yl-r (2) where Y is the fabrication yield and T is the single stuck-at fault coverage. Equation (2) can be employed to find the DL of a testing method, if the yield and fault coverage are both known. Fault coverage is available for deterministic test generation methods or random testing supported by fault simulation [2,7]. Equation (2) also shows that DL is exponentially related to fault coverage.
The deterministic DL analysis of [11] was extended to random testing in [12], which provides an equation relating DL, yield, random test length, and susceptibility. Based on the observations from results of many different examples, it is concluded that random pattern testability is a function of the number of random patterns, and that all examples have the same basic shape. The function describing the basic shape an exponential response as in a RC circuit is then employed to approximate the relationship between fault coverage and random test length by the equation T e -ln(N)/lglcln 10 N -1/lglcln 10 (3) where N is the number of random patterns applied and c is the fault susceptibility constant. Finally, by combining Eqs. (2) and (3), the DL for random testing is derived as DL-g N-1/lOgla'lnlO (4) The curve fitting of random testing using a statistical sampling plan has also been described, and it allows one to deduce the number of random patterns required to give a specified DL with a known yield. Experimental data suggest the validity of the DL model for random testing. Note that c is estimated using fitting methods [12].
In [8], the technique of sequential statistical analysis was employed as a vehicle to derive the relationship among DL, yield, random test length and detection probability. Instead of using the deterministic DL analysis as a bridge as in [12], sequential statistical analysis directly examines the random test behavior and results in a simple derivation for the DL estimation. The susceptibility constant (c0 used in [12] is replaced by the worst detection probability, or, using the single stuck-at fault model. The DL of random testing obtained is given by equation testing based on wafer test data [13]. In this approach, the data on the measured fraction of failing chips versus the number of test vectors is used to empirically determine a failure probability density function. True yield and DL (or reject ratio) can then be estimated without fault coverage or detection probability analysis. Since the tested product quality is directly evaluated from test data, the need for complex fault models and fault analysis has been eliminated. Other important DL analysis methods or practices can be found in [14][15][16][17][18][19][20].
where x is the random test length. The technique of sequential statistical analysis was then extended to pseudorandom testing in which no test patterns can be repeated. It has been established that the DL of pseudorandom testing is no larger than that of random testing, if the CUT is a combinational circuit and faults do not result in any sequential behavior. The DL of pseudorandom testing can be represented by the following equation

WORST FAULT ANALYSIS OF PSEUDORANDOM TESTING
Stochastic analysis has been widely used in sequential circuit testing [21] and built-in selftesting [22]. Theoretically, pseudorandom testing also has stochastic behavior since the detection probability of each pseudorandom test pattern depends on whether its predecessor detects the fault or not. If test pattern tz does not detect faultf, DL-- where M is the total number of input combinations, and/3 is the number of test patterns detecting the worst single stuck-at fault. Due to the complex combinatorial enumeration, the above equation cannot be further manipulated to a closed form [8].
Thus, computer enumeration, which is not only time-consuming but also inaccurate, is resorted to derive the DL of pseudorandom testing. The purpose of this work is to alleviate this difficulty by obtaining a closed form for the DL analysis of pseudorandom testing using stochastic analysis.
All previously mentioned methods estimate the DL of circuit testing in terms of fault coverage or detection probability to reflect the testability of the CUT. It is also possible to analyze the DL of circuit then test pattern ti+l has higher probability of detecting f. Pseudorandom testing can be well described using a discrete stochastic model, since the test patterns are applied one by one. Unfortunately, discrete models generally lead to the difficulty of solving difference equations as in [8].
In this work, we use a continuous stochastic model which results in easily solvable differential equations. This solution is appropriate since the deviation between discrete modeling and continuous modeling can be ignored, if the number of pseudorandom test patterns applied is large. In the BIST design of VLSI circuits, the number of pseudorandom test patterns applied is generally on the order of at least several millions. Thus, the continuous stochastic analysis is very accurate as results demonstrate later.
To simplify the analysis, we introduce some notation and terminology that will be utilized.
Fault Spaces w: w-Wo, wl. The set w denotes whether the CUT is defective or defect-free. Let Wo denote the defect-free circuit condition, and Wl the condition of the circuit being defective. For ease of discussion, a single stuck-at fault model is assumed. However, the general case can be implied. Test Set 7-" 7-tl, t2,... ,tm. 7-is a set of pseudorandom test patterns. Thus, ti-0 or for l<i<m. Detection Set 7" 7--T,T2,...,Tm. If test patterns t,..., tj are applied to the CUT and the circuit fails, that is, the observed outputs are different from those of the fault-free circuit, the value of Tj. is defined to be 1. On the other hand, if test patterns t,..., tj. do not cause the CUT to fail, that is, the CUT produces an output sequence identical to that of the fault-free circuit, then the value of Tj. is defined to be 0.
A Priori Probabilities P(wi), 0 _< _< 1" Here Pi--P(w), 0 _< _< 1, denotes the a priori probability that the circuit is in state wi. In particular, Po-P(wo) is the a priori probability that the circuit is fault-flee, while P-P(Wl) is the a priori probability that the circuit is faulty. The values of the Pi's are assumed to be known, since they can be obtained empirically from the information supplied by the manufacturer, or from experimental data. Note P0+P1-1 and P0 is the fabrication yield Y of a manufacturing process.
Using the above definitions and notations, the defect level of circuit testing can be formulated as Obviously, we have P(Tx=Olwo)= 1. From the above equation, it can be observed that the major difficulty on DL analysis lies in the derivation of P(Tx=Olwl), the escape probability. Instead of using sequential statistical analysis and solving a set of recurrence relations as in [8], we concentrate on dealing with the escape probability analysis, , for x pseudorandom test patterns.
The result is then employed to solve Eq. (7). In order to investigate the fault detection behavior under pseudorandom testing, a stochastic model with two states So and S is established. As shown in Figure 1, So represents the state in which the (worst) fault has not been detected and $1 corresponds to the detection of the fault. We also assume that the total number of pseudorandom test patterns is M, the number of pseudorandom test patterns that have been applied is x, and the worst fault can be detected by/3 pseudorandom test patterns as in [8]. When pseudorandom testing proceeds, state transition probabilities keep changing because no test pattern can be repeated. For example, the state transition probability from So to $1 is (/(mx + 1)) and the probability is increased as more and more patterns are applied (i.e., x is larger and larger). Other state transitions can be discussed similarly.
The following differential equation can be extracted from the Markov model, to describe the relationship of the state probabilities.
The initial condition (i.e., the initial state probabilities) is S0(0)= and SI(0)=0. It should be noted that Si denotes either state or the probability of state without causing confusion. initial condition, is finally given as (9) The detection probability is Sl(x) and the escape probability is So(x), and Sa(x)corresponds to the detection of the worst fault. Thus, we have P(Tx 0]Wl) where DLs denotes the DL value derived using the proposed differential analysis based on the stochastic model. The above representation for the DL analysis of pseudorandom testing is much simpler than its discrete counterpart given by Eq. (6).
Deriving the DL for pseudorandom testing using Eq. (6) is not economical at all, even worse, the numerical error accumulated is not tolerable in large test cases (e.g., M is on the order of millions and a long pseudorandom test sequence has been applied). detectability, yield, the pseudorandom test length applied, and the total number of pseudorandom test patterns, under different circumstances. Equation (11) also reveals that the DL of circuit testing can be reduced by: (1) increasing the fabrication yield, (2) increasing the detectability, or (3) increasing the pseudorandom test length. The fabrication yield can be increased by improving the manufacturing deficiencies, while the detectability can be enhanced using design-for-testability techniques [2]. It appears that enhancing the circuit detectability or applying longer test sequence is more beneficial than increasing the fabrication yield, since the relationship between DL and 3, x is an exponential function (however, the relationship between DL and Y is linear). Of course, design- t=l M-t+l The above discrete solution involves very tedious computational enumerations, which can be very time-consuming and inaccurate. Especially, numerical errors accumulated after million times (or more) of divisions and multiplications will be intolerable. The DL thus derived using the discrete solution can be represented by where DLa denotes the DL derived using discrete analysis. It can be found that the above equation is a simpler form of Eq. (6). To investigate the deviation between the difference and differential solutions, we must concentrate on Eqs. (9) and (12). By the difference solution, the escape probability, So(x), equals 0 if x--M-/3+ 1; and this is the real case for pseudorandom testing. Substituting x--M-3+ into Eq. (9), the escape probability using the differential solution can be represented as M+I (14) It is interesting to find that the above equation approaches 0 regardless of the value of/3, when M is large. This demonstrates that the proposed differential solution is rather accurate around the zero-escape point. Table I   We have also found that the differential solution provides an upper bound for the escape probability of pseudorandom testing. This can be verified by the following lemmas and theorem. Note that the equality condition of the above theorem holds when/3--0, since both sides of the equation give value 1. The reason can be easily explained and is omitted. We can also prove that DLs gives an upper bound for the real case (i.e., the difference solution). This can be easily achieved by applying Theorem to compare Eqs. (11) and (13). The determination of DL depends on two factors: yield and testability. We have found that the deviation between DL and DLa is dramatically shrunk, if the yield is very high. This can be easily verified by comparing the factors of DLa and DL.
Our previous work shows that the DL derived using the random pattern assumption (i.e., test patterns can be repeated) also provides an upper bound for the DL of pseudorandom testing [8]. Using sequential statistical analysis, the DL of random testing has been determined as where DLr denotes the DL of random testing [8].
The worst detectability, /3, can be approximated using the product of a and the total number ofinput pattern combinations (2n, for an n-input circuit) of the CUT. Yield estimation also plays an important role in the DL analysis. Mostly, a rather accurate yield value can be determined by analyzing the defect statistics and test data [29].

K-FAULT ANALYSIS OF PSEUDORANDOM TESTING
Generally, the quality of random testing is considered based on the concept of test confidence [2], and a random test length is determined to achieve the test confidence measured by the probability that the applied random patterns detect every single stuck-at fault [10] or the worst stuck-at fault [30]. The confidences thus determined are called testing quality and detection quality, respectively [2]. Mostly, the random test sequence provided by the embedded BIST device is pseudorandom, and the same set of test patterns is generated and expected to detect all possible single stuck-at faults occurring on each CUT. Thus, the test confidence measured by testing quality is more convincing than that given using detection quality. (1) The pseudorandom test length required for a fault set with a disjoint test set is no less than that for a fault set with a conjoint test set, to achieve the same test confidence [31].
(2) Each fault whose detectability is not smaller than twice that of the worst detectability can be ignored from the test confidence consideration [31].
The above observations are consistent with the results of random test consideration [10]. Based on these two observations, the analysis of DL in terms of testing quality for pseudorandom testing can be greatly simplified.
Consider a disjoint fault set whose members are faults fl,..., fm; and k(k _< m) faults have the worst detectability (or less than twice the worst detectability). To further simplify the analysis, each fault in the fault set is assumed to have detectability equal to the worst detectability,/3. Figure 1))]k. Details of the derivation process for the above differential equations can be found in [31]. The value of Sk(X) gives a lower bound for the detection probability by considering all single stuck-at faults. We emphasize that/3 is the number of different test patterns which detect the worst single stuck-at fault. The escape probability, P(Tx=Olwl), can easily be given as P(Tx=O]Wl)= 1--Sk(X). Finally, the DL of pseudorandom testing, in terms of testing quality, can be represented by the following equation where DLz denotes the DL value determined by considering all single stuck-at faults (in fact, k faults after a series of simplifications). It is interesting to find that the above equation degenerates to the DLs equation of the worst fault case Eq.
It has been an agreement that the single stuck-at fault model is not adequate in representing VLSI defects. In fact, the majority of VLSI defects can not be modeled by single stuck-at faults. The effectiveness of using the stuck-at fault coverage as a predictor of the defect level has been studied by simulating bridging faults on benchmark circuits [32]. Results demonstrate that the predicted DL may differ from the real defect level by as much as an order of magnitude, as the desired DL decreases. Another analysis also concludes that unmodeled faults have significant impacts on defect coverage, and more than 100% single stuck-at fault coverage is required if the DL is intended to be controlled very small [33]. Experimental data announced from HP indicates that using single stuck-at fault coverage as an estimator predicts a much lower (than the actual) DL, when fault coverage exceeds 90% [34]. Although most reports draw unfavorable conclusions to the single stuck-at model, there might be good agreement between the model and actual fabrication data under the right set of conditions [35]. For example, it is possible to achieve a good agreement between the actual and predicted DL, if the stuck-at fault coverage is obtained using functional test patterns [34]. Our DL analysis method has been established based on the single stuck-at fault model, as far as the detectability is concerned. It is interesting to verify the availability of the work, since pseudorandom test patterns have closer relationships to functional test patterns (than to deterministic test patterns). The long test sequence, which achieves high single stuck-at fault coverage, generally has a very high possibility of detecting other unmodeled faults.
Most DL analysis methods use the assumption of uniform defect distribution, i.e., the presence of any particular defect is independent of the presence of other faults. However, defects on a wafer are not uniformly distributed, and tend to exhibit clustering. The spatial defect clustering information can be employed to optimize waferlevel test costs [36]. It also has been found that a faulty chip generally has more than one defects [33]. Multiple faults, which might contain different fault types, occurring on the same chip sometimes result in fault masking behavior [2]. Multiple fault detection has been identified as a very difficult problem in the VLSI testing area, and its influence on DL deserves more attention. The probability of multiple stuck-at fault detection using single stuckat test set depends on the circuit structure, instead of the circuit size. For example, there exists a complete test set for single stuck-at faults that detects all multiple stuck-at faults, if the CUT is fanout-free [37,38]. Though all single stuck-at faults have been considered in this work, the detection of multiple faults and non-uniformly distributed faults on a single chip needs to be further researched. The effect of multiple stuck-at faults under random testing environment has been analyzed in [39].
It is natural that defects generally occur with different probabilities, since critical areas on a chip is more apt to cause defects. To simplify the discussion, a Poisson's model has been assumed for the defect distribution over the chip [40]. The well-known William and Brown defect model [11] has been extended to a more general case by removing the hypothesis of equally likely fault and exploiting the concept of critical area to evaluate the fault occurrence probabilities over the chip [40]. In this work, the worst detectability has been used to estimate the DL for pseudorandom testing. DL estimation using the worst case hypothesis might be pessimistic, since the hypothesis implicitly assumes that all fault occurrences are the worst faults. The results have been extended to consider all single stuck-at faults, and the DL analysis of non-equally likely faults has been considered by weighting different fault occurrence probabilities to the corresponding fault detectabilities. Recent work has indicated that equiprobability hypothesis and other non-equiprobability distributions result in very low difference in random test length estimation, when the fault coverage is high [41]. This might alleviate the difficulty of finding a fault occurrence distribution by assuming that all faults may occur equally likely. Recent work has reported that non-uniform distribution of detected faults has strong impacts on test quality [42]. It has been concluded that fault coverage requirements are significantly higher, if the undetected faults are clustered rather than being uniformly distributed. Thus, the conventional fault coverage which is based on the randomly distributed coverage assumption gives a lower bound on acceptable fault coverage to achieve the expected DL. Since our DL analysis is based on the weighted worst faults, the impact of non-uniform detected fault distribution is less serious. In summary, there are too many factors affecting the accuracies of the DL analysis regardless of the testing techniques employed. Most proposed DL analysis methods have inherent deficiencies, and more researches are required.

CONCLUSIONS
In this paper, the DL analysis of pseudorandom testing has been achieved using a stochastic model. This is the first time to derive a closed form which clearly gives the relationships among DL, detectability, yield, the number of all input combinations, and the applied test length, under pseudorandom testing environments. Results obtained based on the single stuck-at fault model and worst case analysis demonstrate that the DL estimated using continuous stochastic analysis gives a very good approximation to the actual DL value, provided the number of pseudorandom test patterns applied is large. Generally, the pseudorandom test set is very long (at least on the order of several millions), and this makes the proposed solution well fit to many practical applications. The analysis is then extended to consider all single stuck-at faults. A closed form has also been derived to take the number (k) of hard-to-detect faults into account. However, we must emphasize that the k-fault analysis results in a too pessimistic solution and has been relaxed by weighting fault occurring probabilities into the k-fault escape probability. The results obtained are mainly based on the single stuck-at fault model. However, they can be extended to other fault types such as bridging faults, as long as the corresponding detectabilities can be derived [43].
Recently, there have been many reports questioning the assumptions employed in the process of DL analysis. However, the analysis is almost impossible if these assumptions are removed. It appears to us that solutions proposed based on the stringent assumptions still can be used, however, the results must be interpreted with care. Especially, the DL values under very high fault coverage are critical. Fortunately, pseudorandom testing might be immune to this critical region since the long test sequence generally detects many unmodeled, or non-uniformly distributed faults.
Dr. Das published extensibly in the areas of switching and automata theory, digital logic design, threshold logic, fault-tolerant computing, microprogramming and microarchitecture, microcode optimization, applied theory of graphs, and combinatorics. He served in the Technical Program Committees and Organizing Committees of many IEEE and non-IEEE International Conferences, Symposia, and workshops, and also acted as session organizer, session chair, and panelist.  Dr. Das is the 1996 recipient of the IEEE Computer Society's highly esteemed Technical Achievement Award for his Pioneering Contributions in the .fields of switching theory and modern digital design, digital circuits testing, microarchitecture and microprogram optimization, and combinatorics and graph theory. He is also the 1997 recipient of the IEEE Computer Society's Meritorious Service Award for excellent service contribution to Transactions on VLSI System and the Society, and was elected a Fellow of the Society for Design and Process Science, U.S.A. in 1998 for his accomplishments in integration of disciplines, theories and methodologies, development of scientic principles and methods for design and process science as applied to traditional disciplines of engineering, industrial leadership and innovation, and educational leadership and creativity. Dr