Diophantine Frequency Synthesizer Design for Timekeeping Systems

Diophantine Frequency Synthesis (DFS), a number-theoretic approach to the design of very high resolution frequency synthesizers, was introduced in 2006. Further work concerning the impact of controlling mixing products for high-spectral purity was addressed and reported at the 2007 European Frequency and Time Forum. The focus of this paper is on the implementation of nested DFS architectures targeting microphase-type applications for precision timekeeping systems. We have shown that DFS does not impart any extraordinary design constraints on spectral purity in comparison to commonly used high resolution frequency synthesis techniques such as DDS or fractional N . Here we describe a design approach for 10 MHz synthesizers with 1E-13 fractional resolution in consecutive steps ranging ±10 Hz. The synthesizers generate their output from a 10 MHz reference standard. Such synthesizers are essential to accomplishing precision frequency correction in timekeeping systems.


INTRODUCTION
In timekeeping systems, a local frequency and/or phase must be generated and maintained to a very high degree of accuracy. For example, the Time and Frequency Laboratory of the Johns Hopkins University Applied Physics Laboratory maintains UTC (APL) within ±10 nanoseconds, based on monthly reports from the Bureau International des Poids et Mesures (BIPM). Modern timekeeping systems use phasefrequency correction (steering) through auxiliary synthesizers to maintain the accuracy of their master clocks to UTC. The frequency step resolution of synthesizers for steering timekeeping systems is typically 1 μHz or better. Designers of these very fine resolution synthesizers must carefully consider signal purity, resolution (accuracy to the global reference), and complexity. Our paper describes the Diophantine Frequency Synthesis (DFS) design approach for very fine frequency resolution synthesizers suitable for the maintenance of autonomous clock holdover and microphase steering in laboratory timekeeping systems.
The novel DFS approach was introduced in 2006 [1,2]. We have found that DFS alleviates the conventional trades in performance for frequency synthesizer design without sig-nificantly taxing system complexity or resources. DFS provides high spectral purity, even in synthesizers with much less than 0.1 PPM resolution steps. In general, we make this claim in comparison with other fine resolution frequency synthesizer methods such as Direct Digital Synthesis (DDS) or fractional-N modulators which are known to present a high degree of unwanted spurious signals into the output spectrum through the fundamental process that they impart on the input reference signal [3]. The use of DDS and fractional-N synthesis design techniques has been widely adopted for timekeeping systems as high-frequency resolution (accuracy) and fast acquisition (settling time) can be achieved without the complexity of traditional multiple loop synthesizers. However, DDS and fractional-N synthesizers both cause phase perturbations in their basic operation schemes leading to coherent spurious generation [3]. In the case of DDS, accuracy to a desired frequency necessarily compromises the spectral purity of the output signal by the incidence of truncation spurious attributable to the finite size of sin/cos lookup table and the DAC [4].
DFS uses only exactly periodic signals, without employing dithering, interpolation, pulse removal, or any other approximately-periodic waveform that may corrupt the 2 International Journal of Navigation and Observation spectrum close to the carrier. DFS-based synthesizers present no discontinuity of the reference frequency phase, such as DDS or fractional-N, and unlike these methods, DFS does not require any special devices such as high-resolution DACs, accumulators, or sigma-delta modulators to control the spurious level of the output signal.
However, like traditional multiple loop PLL synthesizer architectures, DFS does require mixing (or multiplication) to achieve the output signal. This means that DFS synthesizers can suffer from unwanted spurious if attention to the circuit design is not adequately respected. In our 2007 EFTF paper, we described an approach for the design of VHF synthesizers with high-spectral purity of >100 dB spurious free dynamic range and showed that DFS presents no unique design-related constraints [5]. Rather, DFS design flexibility provides an advantage to achieving this level of performance in fine resolution frequency synthesis.

DFS-ELEMENTS OF THE THEORY
DFS is a number-theoretic approach to frequency synthesis. It is based on mathematical properties of integer numbers and linear Diophantine equations [2] (by definition, a Diophantine equation is an algebraic equation whose solutions are required to be integers [6]). DFS results in high-level architectures using two or more Integer-N PLLs. It distributes the desirable output-frequency resolution among these constituent PLLs in such a manner that the resultant output fractional-frequency resolution is equal to the product of the constituent PLLs' fractionalfrequency resolutions. Consequently, this property of DFS allows for the output frequency resolution to be made (arbitrarily) fine, that is, to have a very small frequency step, without using large prescalers or low phase-comparator frequencies in the PLL.

The abstract DFS concept
DFS considers a PLL as a multiplier of an input frequency f in by a rational number m i /N i , as shown in Figure 1.
In Figure 1, two PLLs (i.e., two multipliers by m 1 /N 1 and m 2 /N 2 ) are driven by the same reference frequency f in . Their output signals are mixed (and the mixer's output is filtered -not shown) to produce the synthesizer's output signal of frequency f out which typically is f out = f 1 + f 2 , as it is here, or f out = f 1 − f 2 . Further discussion on mixing follows in Section 3.
As it is always the case with integer-N PLLs, the frequency resolution (step) of the individual PLLs in Figure 1  equals PLL's phase-comparator frequency, that is, f in /N 1 and f in /N 2 , respectively. Therefore, to get smaller frequency steps (higher resolution) from a single PLL, a larger prescaler N i and/or lower reference frequency f in are required. This, necessarily results in a lower phase-comparator frequency f in /N i implying slowed frequency lock acquisition (agility) and potentially increased spurious signal levels closer to the carrier signal of f out [3]. DFS overcomes these problems as it allows simultaneously for both high phase-comparator frequencies at the constituent PLLs and arbitrarily small frequency step at the output of the synthesizer. In the case of DFS scheme in Figure 1, the frequency step is which can be orders of magnitude smaller that f in /N 1 and f in /N 2 . This property of DFS is generalized in the case of k PLLs. Throughout this paper, the prescalers (N i 's) of the PLLs are considered fixed in size. Moreover, it is assumed that by design, the greatest common divisor of every pair of prescalers, (N i , N j ), is one , that is, the prescalers are pairwise prime integers; this is a requirement of the DFS methodology [2].
Finally, it is convenient to replace the value of every feedback divider m i by the sum m i + m i (e.g., as in Figure 2), where m i is a fixed positive integer and the variable part, m i , is restricted to take integer values within the range −N i to N i . So the range of values of the feedback divider is

Basic numerical example of a two-PLL DFS scheme
Consider the architecture of Figure 2 consisting of two PLLs driven by the same reference frequency f in , whose output frequencies are summed resulting in Following DFS methodology [2], the prescalers, N 1 = 3 and N 2 = 2, are fixed and relatively prime by design (small integers were selected here for illustration purposes).
The feedback dividers are 11 + m 1 and 9 + m 2 with −3 ≤ m 1 ≤ 3 and −2 ≤ m 2 ≤ 2. So, the range of each PLL feedback divider is twice the size of the corresponding prescaler. These imply that frequency f 1 can take any of seven values f 1 ∈ {8/3, 9/3, . . . , 14/3} and frequency f 2 can take any of five values f 2 ∈ {7/2, 8/2, . . . , 11/2}. Table 1 shows (some of) the output frequencies f out that can be generated by using the DFS algorithm in [2] to program the values of m 1 and m 2 within their preassumed ranges −3 ≤ m 1 ≤ 3 and −2 ≤ m 2 ≤ 2, respectively. Every one of the thirteen triplets (m 1 , m 2 , a) in Table 1 satisfies the linear Diophantine equation This way we can synthesize all frequencies of the form with the variable a taking the values −6, −5, . . . , 6 and the central frequency f out being Note: the phase comparator frequencies of the individual PLLs are f in /3 and f in /2 while the synthesizer's frequency resolution (step size) is f in /6.
In general, a two-PLL DFS synthesizer results in output frequency where the variable a can take any of the consecutive values from −N 1 N 2 to N 1 N 2 . This leads, by inspection of (6), to the fundamental property of DFS that the frequency step can be made much smaller than the phase-comparator frequencies the constituent PLLs, that is, Expression (6) itself results from our ability to find a convenient solution of the linear Diophantine Equation Note that the relationship between m 1 , m 2 , and a, governed by (8), is nontrivial and in some cases is not unique, in the sense that there may be more than one pair of integers (m 1 , m 2 ) that solve (8) for a particular value of integer a.
Furthermore, it has been proven that if we have a solution (m 1 , m 2 ) of (8) for a = 1, then we can easily generate solutions for every other value of a; therefore in a hardware implementation, very few numbers have to be stored. A detailed description of how to solve linear Diophantine Equations efficiently is also available in [2].

DFS synthesizers with k PLLs
The general abstract high-level architecture of k-PLL DFS synthesizers is shown in Figure 3.  It has been proven, in [2], that when the integer variables m 1 , m 2 , . . . , m k are allowed to take any values in the intervals −N 1 ≤ m 1 ≤ N 1 , −N 2 ≤ m 2 ≤ N 2 , . . . , −N k ≤ m k ≤ N k , respectively, then the following set of frequencies can be synthesized: where a can take any of the values and the central frequency f out is Therefore, the frequency resolution (step) achieved by k-PLL DFS architectures is The central frequency f out can be adjusted with resolution δ f out as well. The mathematical details, theorems, and their proofs of the general k-PLL DFS architectures can be found in [2].

FREQUENCY-OFFSET DFS ARCHITECTURES FOR VERY HIGH FRACTIONAL-FREQUENCY RESOLUTION
Synthesizers with very high fractional-frequency resolution like microphase steppers, advanced signal generators, certain instrumentation equipment, atomic-clock synthesizers, and so forth, often have performance specifications that challenge existing technology solutions especially under cost, power, size, and complexity constraints. DFS offers a new alternative to DDS and fractional-N PLLs in the design of such systems. For this kind of applications, most appropriate DFS architecture has been proven to be the one based on frequency offsetting [3]. Since frequency offsetting requires mixing, a few comments are in order without any intention to cover the topic of mixing.

Frequency mixing
Mixing of two periodic signals at frequencies f 1 and f 2 is denoted by ⊗, see Figure 4, and the outcome is typically chosen to be either f 1 + f 2 or f 1 − f 2 .
Mixing of three or more signals has a similar interpretation, note however that the order of performing the mixing of the signals may be important for getting a spectrally pure output signal. In general, minimization of mixing spurs involves the choice of the central frequencies of f 1 and f 2 , their frequency ranges, the choice of the sum or difference, the harmonic contents of the mixed signals, and of course the type of the mixers.
The key to low-output spurs in DFS synthesizers is the mixing method since the mixers are the dominant spurs generating circuit elements.

Frequency offsetting
The synthesizer architecture in Figure 4 is convenient for deriving the sum or difference between a large f in and a small offset frequency f .
When f / f in 1, the mixing of f in with f in ± f can be performed without difficulty and the mixing spurs can be minimal, for example, [5]. Therefore frequency offsetting is an effective approach to achieving the frequency summations and/or subtractions needed to realize DFS with central output frequency close to f in .
The following subsections illustrate this approach for the case of two-and three-PLL DFS schemes. In principle, the structure of Figure 4 can be cascaded k times to create k-PLL DFS architectures. Figure 5 shows how two DFS-determined PLLs can be cascaded using an offset synthesizer structure to form a DFS architecture, where the variable f out can be adjusted in very small-frequency steps from the reference f in .

Two-PLL frequency-offset DFS architecture
Based on the DFS theory [2], the two PLL output frequencies f 1 , f 2 (we can consider divider R as part of the PLLs) are determined by the common dividers Q, R, the two relatively prime integers N 1 , N 2 , and the feedback dividers pN 1 + m 1 and pN 2 + m 2 which are partitioned into the fixed, pN 1 , pN 2 , and the variable, m 1 , m 2 , parts. The values of m 1 , m 2 program the value of parameter a in expression (6). The fixed integers pN 1 and pN 2 partially define the central frequencies f 1 , f 2 of the PLLs. In this application, we also like to have f 1 = f 2 which implies that f out = f in when m 1 = m 2 = 0.
Variables m 1 and m 2 are allowed to take any value within their ranges −N 1 , . . . , N 1 and −N 2 , . . . , N 2 , respectively. This results in output-frequency resolution equal to δ f out = f in / (QRN 1 N 2 ) and output-frequency range (equal to or greater than) Δ f out = ± f in /(QR). (Note the product of N 1 and N 2 in the denominator, in contrast to Q that is accounted for on its first power.) The factor Q in the denominators determines the pullability ranges of the VCOs in the PLLs. Specifically, given the ranges of m 1 and m 2 , the VCO's fractional pullability is PL PLL 1,2 = ± (100/Q) %. The role of p in the numerators is to adjust for the central output frequencies of the PLLs by counterbalancing Q. The phase-comparator frequencies of the PLLs are f PC PLL i = f in /(QN i ), i = 1, 2.
Finally, R is a large divider necessary to generate the relatively small frequencies f 1 , f 2 from the output frequencies of the PLLs. Divider R also contributes to the output resolution of the synthesizer and the spectral purity of signals entering the frequency-offset blocks.
Step: Figure 5: Two-PLL frequency-offset DFS scheme. Figure 6: Numerical example of the two-PLL frequency-offset DFS scheme in Figure 5.
With a microphase stepper application in mind, Figure 6 shows a choice of values for N 1 , N 2 , R, Q, and p, and the corresponding characteristics and performance of the synthesizer they result in. A resolution of 10 μHz is probably the best that the two-PLL scheme with 10 MHz input frequency could give. Note that although the 100 Hz frequency offset is not uncommon in these types of systems, a higher frequency would be helpful. The pullability range of ±10% is achievable by tunable LC oscillators, and because of the large divider R, the phase noise of the oscillators is not a critical issue.
As described in Figure 6, the magnitude of R was made large compared to Q, N 1 , and N 2 to achieve the desired frequency-step resolution of ±10 μHz while keeping the PLL phase-comparator frequencies relatively large and easy to filter. This choice was not directed through any fundamental constraint in the DFS method, but was made from our design emphasis on high-spectral purity over acquisition speed in a simple, practical circuit implementation. In the following subsection, we see how adding one more PLL allows for more choices of the parameters and, in principle, better overall performance.

Three-PLL frequency-offset DFS architecture
A three-PLL frequency-offset DFS architecture is shown in Figure 7. Its principles of operation are very similar to those of the two-PLL one in Figure 5. The major difference is that because of the odd number of PLLs, centering f out with respect to the input reference f in requires further design consideration.
Specifically, it is desirable that m 1 = m 2 = m 3 = 0 implies f out = f in . To achieve this, we add f 1 and f 2 to f in and subtract f 3 . Moreover, we introduce factors of 2 in PLL 3 and in the Rdividers of PLLs 1 and 2. These result in 2 f 1 = 2 f 2 = f 3 = p f in /(QR) and equal ranges of f 1 , f 2 , and f 3 . However, the pullability range of PLL 3 is the half of that of PLLs 1 and 2.
The expression for f out is shown in Figure 7.
Again, with a microphase stepper application in mind, Figure 8 shows a choice of numerical values for N 1 , N 2 , N 3 , R, Q, and p, as well as the corresponding characteristics of the resulting synthesizer. Output frequency resolution of 1 μHz and output range of about ±16 Hz are achieved. The frequency offset has been raised to 500 Hz for PLLs 1, 2 and to 1000 Hz for PLL 3, and the pullability ranges have dropped to about ±3% and ±1.6%, respectively. Therefore, as expected, the three-PLL case provides much more flexibility in the design and much better characteristics.

SUMMARY
In summary, the general structure of DFS architectures provides the following desirable properties: the ability to achieve a predetermined center frequency with frequency range and frequency step (resolution) of while the phase-comparator frequencies of the constituent PLLs are The application of DFS permits high flexibility on the relationship of the fixed-frequency reference to output frequency (9) with wide-frequency range (14). Based on (15), we have shown the design of very fine frequency resolution using two-and three-PLL nested DFS frequency-offset loops.
In the case of the three-loop system described in Figure 7, a fractional frequency synthesizer capable of 1E-13 has been numerically demonstrated. The method of cascading nested frequency-offset DFS architectures to higher orders would ultimately result in frequency steering resolution approaching 1E-15, consistent with the needs of most precision timekeeping laboratories contributing to UTC.