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A new structure for an exclusive-OR (XOR) gate based on the resonant-tunneling high electron mobility transistor (RTHEMT) is introduced which comprises only an RTHEMT and two FETs. Calculations are done by utilizing a new subcircuit model for simulating the RTHEMT in the SPICE simulator. Details of the design, input, and output values and margins, delay of each transition, maximum operating frequency, static and dynamic power dissipations of the new structure are discussed and calculated and the performance is compared with other XOR gates which confirm that the presented structure has a high performance. Furthermore, to the best of authors' knowledge, it has the least component count in comparison to the existing structures.

Resonant-tunneling diodes (RTDs) are of interest for use in different applications [

The most significant part of a multiplier is adder. XOR gate forms the fundamental building block of full adders, therefore, improving the speed of XOR gate can lead to significant increasing speed of the entire system. The XOR function widely used in ALUs, digital encryption systems [

In this paper, a new structure for two-input XOR based on RTHEMT is presented. It comprises only two depletion mode FETs and an RTHEMT. It is the first time, to the best of the authors’ knowledge, an XOR gate based on the RTHEMT is proposed. The characteristics of the proposed XOR gate are calculated by employing a new SPICE model for simulating RTHEMT. The remainder of this paper is structured as follows. In Section

Designing new XORs is of much attantion because they are the main part of an ALU and other digital devices. Different structures and designs were presented in literature for XOR gates over the years. Most of XOR gate circuits are based on FET transistors [

Wang et al

Designing two different XOR gates with six transistors (The figure selected from [

Figure

Bui et al

Designing an XOR with four transistors (the figure selected from [

Chen et al

XOR based on controlled quenching of series connected negative differential resistance (NDR) devices (the figure selected from [

In this paper, a new XOR gate circuit based on RTHEMT is presented. In this section, the RTHEMT and its modeling in SPICE simulator are introduced at first, then details of the design procedure for the new XOR in three subsections are discussed and finally the performances of the gate are drawn.

“An InP-based resonant-tunneling high electron mobility transistor (RTHEMT) incorporates a pseudomorphic InGaAs/AlAs/InAs RTD into the source of an InGaAs/InAlAs high electron mobility transistor (HEMT)” [

(a) Epitaxial structures of RTHEMT, (b) Isolated RTD ^{2} (all figures selected from [

In order to use RTHEMT device in circuit analyzing and simulating the desired circuits, a SPICE model is needed. As discussed in the literature, there are two major categories for simulating RTD circuits: the physics-based models and the nonphasic-based models [

(a) Interior design circuit for modeling RTHEMT. The HEMT characteristics are: Level = 2, ^{2}. (b) Solid line and dotted lines show a RTD and a FET

Current density waveform of RTHEMT and its nearly flat valley current that are shown in Figure

The new two-input XOR gate based on RTHEMT. The RTHEMT charactrestics are the same as Figure

The design is based on 90 nm HEMT technology. Since the original paper [

Solid line shows the new RTHEMT characteristics (by employing 90 nm technology) and two other lines show two load lines with

As an intermediate step and before final design, we replace the FETs, which are shown in Figure

In this step four following variables are defined:

We add another limitation so that the input margins for low and high logics should be equal to each other (

By considering the three last equations, there would be only one degree of freedom for selecting the four mentioned variables that we use this one for generating a good margin in the output, consequently, the below values are assigned to variables:

Figure

The output gate current (vertical axis) as a function of two input voltages

As a last step we rereplace the resistors with two depletion mode transistors in order to achieve the original design. These transistors lead to high scaling and occupied less area in a chip in comparison to resistors. The final design scheme is depicted in Figure

The proposed gate which is designed in previous section is simulated in the SPICE simulator by using the presented model with

(a) Seven different input voltage transitions and (b) output simulation result waveform in current mode with

(a) Summation of power of sources in the circuit including input waveform generators and bias sources (

Table

Static power dissipation.

State | Static power ( |
---|---|

For each two-input gate, there are twelve transition possibilities; however, for a gate with symmetric inputs, number of transitions reduces to seven distinct transitions. Figure _{T}

Dynamic energy dissipation and delay for seven different transitions.

Number | First state | Second state | Transition energy ( | Delay (picoseconds) |
---|---|---|---|---|

1 | ||||

2 | ||||

3 | ||||

4 | ||||

5 | ||||

6 | ||||

7 |

The transient latency for seven different transitions is shown in fourth column of Table

As stated before, the maximum delay is happened in response to 11 to 01 transition and is equal to 11 picoseconds. Therefore, the maximum frequency of the gate is

Figure

The calculation results demonstrate that static power dissipation (

The comparison between proposed XORs.

Input voltages and margins | Output margine | Number of components | Performance | Design consideration | |
---|---|---|---|---|---|

6-transistor XOR | High Logic: 5 V | Not mentioned | FET : 6 | Simulation results up to 50 MHz, Maximum delay: | There are two types of implementation with different characteristics |

Low Logic: 0 V | Figure | ||||

Figure | |||||

4-transistor XOR | High Logic: 3.3 V | Not mentioned | FET : 4 | Simulation results up to 200 MHz, delay: 350 picoseconds | No power supply (powerless design) |

Low Logic: 0 V | |||||

Quenching of series-connected NDR devices | High Logic | Not mentioned | RTD : 3 | Not mentioned | For the XOR function, two FETs can be eliminated by exact design of each RTD area |

Low Logic: 0 V | FET : 6 | ||||

RTHEMT XOR (This paper) | High Logic: 1.1–1.4 V | High logic: | FET: 2 | Max Freq: 90.90 GHz | 1. One state has nearly zero static power dissipation. |

Low Logic | Low Logic | RTHEMT: 1 | Max Delay: 11 picoseconds | 2. In highest frequency it dissipates only |

In this paper, a new XOR logic gate based on RTHEMT is presented. To the best of our knowledge it is for the first time that an RTHEMT-based XOR logic gate is presented. In different subsections, the characteristics of the gate including dynamic and static power consumptions and delays are fully covered. In addition, the results were drawn by employing a new subcircuit model for simulating RTHEMT in SPICE. The simulations demonstrate that most features of the proposed XOR gate circuit have superior performance in contrast with other structures. The comparison between the new XOR gate circuit and other ones is summarized in Table