One Clock-Cycle Response 0.5 μm CMOS Dual-Mode ΣΔDC-DC Bypass Boost Converter Stable over Wide RESRLC Variations

Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy. The frequency-compensation network, however, limits speed and regulation performance because it must cater to all combinations of filter capacitor CO, inductor L, and CO’s equivalent series resistance RESR resulting from tolerance and modal design targets. As such, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even if the likelihood of occurrence of the latter is considerably high and the former substantially low. Sigma-delta (ΣΔ) control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide RESRLC compliance in boost converters. This paper presents a dual-mode ΣΔ boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dump events was experimentally 1.41 to 6 times faster than the state of the art in current-mode ΣΔ boost supplies, and this without any compromise in RESRLC compliance range (0–50 mΩ, 1–30 μH, and 1–350 μF).


Introduction
In portable applications like cellular phones, PDAs, and the like, integrated BiCMOS and CMOS switching dc-dc supply circuits reduce cost, size, component count, and design complexity (from a user's perspective). One of the critical bottlenecks in obtaining a fully integrated solution, however, is the frequency-compensation circuit, which is designed around off-chip power LC filter devices to obtain optimal performance [1]. The fact is mode-rich state-of-theart applications, manufacturing tolerances, and parameter drifts expose dc-dc converter integrated circuits (ICs) to wide variations in output capacitance C O , power inductance L, and C O 's equivalent series resistance R ESR , inducing considerable changes in loop-gain and transient response, compromising feedback stability or transient response. As a result, to guarantee stability and high bandwidth with a fixed on-chip frequency-compensation circuit, the design necessarily constrains R ESR LC values within a narrow target range [1]. This is especially detrimental in compact highperformance multiple input-output converters [2,3], where the on-chip or in-package LC filter is variable by design to dynamically accommodate the diverse loading conditions of the system.
Unclocked or asynchronous sigma-delta (ΣΔ) buck converters [4][5][6][7][8] are self-compensating and free of the speedstability tradeoffs of most dc-dc converters because the control loop in these converters resembles current-mode control by indirectly sensing the inductor current ripple via the ripple voltage it drops across C O 's R ESR . In other words, the ESR voltage mostly sets the terminal ripple voltage of C O , impressing the inductor ripple current information on the output voltage and achieving current-mode-like control. The resulting single-pole-like response yields higher bandwidth and more explicit control over the output ripple voltage [7].

Advances in Power Electronics
Extending this technique and its benefits to boost converters, which are popular in portable electronics for boosting battery voltages to 3.3-5 V, is not straightforward because the inductor current does not fully flow to C O . Consequently, in realizing ΣΔ control in boost converters, the feedback circuit must explicitly sense and mix inductor current with the sensed output voltage [9]. Such techniques, however, resurrect the limiting speed-stability tradeoffs ΣΔ control averted in buck converters in the first place, forcing the designer to adjust current and voltage gains thereby reducing the loop bandwidth in order to accommodate large R ESR LC filter values.
This paper presents a dual-mode boost ΣΔ bypass controller IC that overcomes the aforementioned speedstability compromise by introducing a high-speed bypass mode (and circuit) that engages only during transient loaddump events, achieving both high bandwidth and wide R ESR LC compliance. To this end, Section 2 first reviews and discusses the stability requirements of ΣΔ converters and their resulting transient response to fast load dumps. Section 3 then describes the proposed dual-mode technique and the design of its IC-prototype embodiment, followed by experimental results in Section 4; Section 5 draws relevant conclusions.

ΣΔ Control in Buck Converters.
A ΣΔ buck converter, as shown in Figure 1, controls the frequency and duty cycle of PMOS switch S M by comparing rippling output voltage v O via sensed voltage v S against dc reference V REF with comparator CP V . Operationally, ac inductor ripple current i l flows into C O and its R ERS (which is relatively large in these converters at 100-250 mΩ to ensure its voltage -v esr -overwhelms ac capacitor voltage v c ) [7] as capacitor displacement current i c , forcing ac output ripple voltage v o to mimic i l (v o ≈ v esr =i l R ESR ). As a result, in regulating v o , the converter also regulates i l , which in the process simplifies the frequency response of the converter to that of a single-pole system, as in current-mode control, guaranteeing stability, irrespective of R ESR LC values.
In  [8]. In other words, only the inductor and capacitor slew-rate limits and second-order delays across the comparator and switch set the response time (effective bandwidth) of the system. Note a negative load dump undergoes a similar but reversed response.

ΣΔ Control in Boost
Converters. Unlike buck converters, ac inductor ripple current i l in boost converters does not flow completely to output capacitor C O because reversebiased diode D (shown in Figure 2) temporarily disconnects L from v O (and C O ) when switch S M conducts all of i L to ground. The resulting ac ripple voltage in v O does not fully reflect the behavior of i l , as it does in buck converters with nonnegligible R ESR values, which means that ΣΔ control in boost converters cannot rely on v O alone [9]. The negative feedback loop in a boosting supply must therefore sense, scale, and mix i L with v O explicitly (e.g., mix i L R I g mi and v O g mv into R S as scaled sum v SUM ) to achieve current-modelike control characteristics. A hysteretic comparator then modulates S M 's frequency and duty cycle based on how the scaled sum (v SUM ) of the ripples compares against a userdefined hysteresis window. Note the voltage feedback loop modulates the effective inductor reference current v I.REF /R I , which is also the average inductor current I L (or low-pass filtered -LPF-version of i L ) to whatever is necessary to fully supply i O .
Within the context of averaged small-signal analysis, the relatively high-gain, low-bandwidth voltage control loop (V Loop) of the system effectively embeds a higher bandwidth, lower gain current loop (I Loop), as shown Figure 3 [10]. At low frequencies, below low-pass filter pole p LPF , i L R I nearly equals v I.REF and the gain of the current loop is practically zero, but increasing with frequency until reaching its highest possible gain at frequencies past p LPF . The current loop's gain again drops at high frequencies, past the complex LC double poles, when the ac voltage across L decreases. Given that i L is, for all practical purposes, regulated to higher frequencies and therefore is a current source to the outer voltage loop at moderate-to-high frequencies, C O and effective load resistance R O set the dominant low-frequency pole of the system while L and R O invoke right-half plane zero z RHP [11].
For stable conditions to prevail, the unity-gain frequency of the voltage loop (i.e., the system -f V.0 dB -) must fall below z RHP and i L must remain a current source (i.e., current loop must stay closed with considerable loop gain) for the frequency range of interest to the voltage loop [10]. As such, f V.0 dB must stay below both z RHP and current-loop bandwidth f I.0 dB : or where D M is the duty-cycle of S M , D M is (1−D M ), and M is the modulator gain. Note that z RHP and f I.0 dB shift to lower frequencies with increasing inductance values, which means that f V.0 dB must also decrease accordingly, in an ideal case. LPF pole p LPF , whose location indicates the lowest frequency at which the current loop is closed, must also be below Advances in Power Electronics Figure 1: Circuit schematic of a switching ΣΔ buck converter. the worst-case value of f V.0 dB to ensure there is enough gain for i L to remain a current source: Ultimately, the system responds to a load dump at the speed of the voltage loop, whose bandwidth is f V.0 dB , allowing switch S M to cycle multiple times before restoring v O back to its target window. LPF pole p LPF limits the extent to which i L naturally responds to a load dump by allowing moderateto-high frequency ac error-correcting signals through the current loop. In other words, the current loop limits (while attempting to regulate) the rising and falling rates of average 0 dB and p LPF both decrease with increasing L, with the former also decreasing with decreasing C O , the worst-case LC combination, from the perspective of stability, occurs at the highest L and lowest C O , the condition for which gains R I g mi R S and g mv R S and pole p LPF are adjusted and transient-response performance over the entire LC filter range is sacrificed.

Proposed Dual-Mode ΣΔ Controller IC
The proposed ΣΔ boost controller IC in Figure 4 overcomes the transient-response degradation associated with the worst-case LC combination by bypassing the main voltage loop (and its f V.0 dB ) with a fast (and lower low-frequency loop gain) feed-forward path only during transient events.
The stability requirements of the main loop set the acceptable R ESR LC range for the system while the high-bandwidth bypass path allows the system to respond in one cycle at the maximum possible inductor current slew rate, the response of which is similar to ΣΔ buck converters. The transient improvement is achieved on chip (i.e., without an off-chip frequency compensation circuit) and without sacrificing LC compliance.

Steady-State and Bypass
In the bypass mode, however, independent loops regulate i L to a value higher than I L(nom) and sensed output voltage v S to V REF , as depicted in the equivalent circuit of Figure 5. The current loop, which modulates switching frequency f SW and S M 's duty cycle d M , has higher bandwidth and appears as a current source for frequencies of interest to the lower bandwidth bypass voltage loop controlling auxiliary switch S A . In the bypass mode, inductor current i L is regulated at a value I PK or V PK /R I that is greater than I L(nom) (i.e., I L required to support I O ). This means, unless otherwise limited, average diode current I D is now higher than I O , as a result of which C O recharges quickly. Once v O is back within the hysteretic window limit of bypass comparator CP B and about to surpass its upper boundary, CP B and S A divert excess current away from D through S A until i O again discharges v O to CP B 's lower window limit. The switching cycle repeats as average inductor current I L gradually drops back to I L(nom) , at which point the bypass loop stops switching and S A remains open. Note as long as I L exceeds I L(nom) , the bypass voltage loop, by independently regulating v O with higher loop gain than the current loop, ensures that the voltage inputs of summing comparator CP S are virtually short-circuited (i.e., v S ≈ V REF ), as shown in Figure 6, allowing CP S to regulate i L exclusively. 4 Advances in Power Electronics

Bypass voltage loop Bypass current loop
Mode transition With respect to stability, as already mentioned, the unitygain frequency of the current loop ( f I.0 dB ) must exceed that of the bypass voltage loop ( f B.0 dB ) so the inductor appears as a current source in the voltage loop, eliminating the complex conjugate pair associated with LC in the voltage loop [12]. Because the unity-gain bandwidth of a ΣΔ loop is its switching frequency, S M 's switching frequency ( f I.0 dB ) must exceed that of S A ( f B.0 dB ). Therefore, since f I.0 dB depends on the rising and falling rates of i L R I as it traverses CP S 's hysteretic current window H I , to force f I.0 dB to be greater than f B.0 dB , C O must exceed where the R 1 -R 2 divider represents the effect of the resistive feedback factor on H V and C O(min) the minimum stable output capacitance.

Transient Response and Mode Transition.
During a positive load-dump event, when I O suddenly rises and v O droops in response, as shown in Figure 7, the dual-mode converter enters its bypass mode, raising i L to peak value I PK (or V PK /R I ) in a single switching cycle of Figure 4 Note that the ratio of L and C O sets the dominant part of Δv O . Once sensed output voltage v S is within the hysteretic voltage window of CP B , to transition back to steady state, i L(avg) must somehow fall back to whatever value (I L(nom) ) is necessary to sustain I O , reducing to zero the amount of excess current i L that bypass comparator CP B steers away from v O through S A . To that end, introducing a series negative offset voltage V I.OS , as shown in Figure 8  Note that the transition is continuous, allowing S A to stop switching without incurring irregularities in S M . During a negative load dump, when i O suddenly drops, as also shown in Figure 7, i L(avg) automatically exceeds its new steady-state target and v O rises above its target. As a result, bypass comparator CP B engages and diverts current away from v O until v S again drops to V REF -H V /2 (in one cycle of S A ). The circuit gradually transitions back to steady state in the same manner as described earlier, through V I.OS .

IC Design.
The proposed dual-mode ΣΔ bypass converter was designed, fabricated, and evaluated using a 0.5 μm, 5 V CMOS process. The circuit embodiment of the converter, as shown in Figure 9, employs a differential-signal processing scheme to attenuate the effects of substrate noise on the high-bandwidth ΣΔ loops [10]. For simplicity, series resistor R I senses i L with the understanding more power efficient techniques are possible and recommended [13]. Currentsense amplifier A DI , which monitors the voltage across R I , includes an internal RC filter that generates differential current reference v I.REF . Differential preamplifier A DV buffers and amplifies sensed output voltage v S by 5V/V to decrease the effects of offsets and hysteretic window limits in posterior amplifiers and comparators on v S and v O (i.e., improve accuracy); A DV drives differential summing amplifier A DS , bypass hysteretic comparator CP B , and transient-detect hysteretic comparator CP B .
For ease of design and reliability, main, bypass, and transient-detect comparators CP M , CP B , and CP T adopt the same circuit architecture, which is designed to yield a hysteretic window of 140 mV. The bypass threshold voltage (ΔV BP ) is composed of half the comparator hysteretic window plus an additional offset of 50 mV (V V.OS ) that is added between CP B and CP T . Differential current-sense amplifier A DI includes a 40 mV offset voltage (V I.OS ) at its output to ensure i L is below its target by V I.OS /R I during the bypass mode, to gradually transition back to steady state after a load dump. The designed offsets are sufficiently large to dwarf the transistor mismatch-induced offsets in A DI , CP B , and CP T and ensure that the polarities of V V.OS and V I.OS remain unchanged across process and temperature corners.
In the absence of deep-N or buried layer isolation structures, the bulk of a single PMOS transistor serving the function of auxiliary switch S A could not be connected to the highest potential (v O ) because of latch-up concerns. Whenever the switching node flies above v O following the turn-off of S M , S A 's body diode can conduct engaging the parasitic vertical PNP transistor present, channeling considerable current to the substrate. A second PMOS device is therefore added in series to use its reverse-biased body diode to block the foregoing current. And during normal operating conditions, when v O is higher than V IN , as the body diode of the first blocks the current of the second.
The proposed ΣΔ controller 0.5 μm IC was designed to supply power from a 2.7-4.2 V Li-Ion battery and drive a 0-1 A load at 5V ± 5% with as wide an R ESR LC range as possible (0-50 mΩ, 1-30 μH, and 1-350 μL was achieved). The total silicon surface area the IC occupied was 1.9 × 2.6 mm ( Figure 10). The peak efficiency of the converter was 93% at 0.4A with a biasing quiescent current of 1.5 mA. The total output voltage variation of the converter in response to a 0.1-1A load dump (Δi O ) with 5 mΩ, 5.6 μH, and 53 μF of R ESR LC was 200 mV, which constitutes a 4x improvement over its nonbypassed counterpart under similar conditions (800 mV).

LC Compliance.
The measured R ESR LC space for which the converter was stable is 0-50 mΩ, 1-30μH, and 1-350 μF, as illustrated in Figure 11. This range was determined by subjecting the converter to 0.1-1A load dumps with 100 nanoseconds rise and fall times. The stability limit was observed as a loss of regulation for the proposed ΣΔ converter in the bypass mode, as the bypass loop was no longer able to control the loop, and subharmonic oscillations for the nonbypassed (state-of-the-art) ΣΔ boost converter [14].
The The maximum capacitance was limited to 350 μF as a practical limit for the intended portable application space (the circuit is stable at higher C O values). Similarly, the maximum R ESR value was limited to 50 mΩ to keep the output voltage ripple acceptably low under a 1 A load. Under these conditions and constraints, the stability spaces for the proposed and the state-of-the-art converters are approximately equal in "volume." Figure 12  in one switching cycle of S M , the state-of-the-art circuit increases i L gradually, pulling v O back to regulation in several cycles of S M , which is why the proposed solution exhibits a fourfold improvement over its predecessor. In a negative load-step (Figure 12(b)), while the excess inductor current is immediately bypassed by switch S A in the proposed converter keeping the output voltage overshoot low (<75 mV), the excess inductor energy causes a large voltage overshoot (600 mV) in the state-of-the-art converter.

Transient Load-Dump Performance. As shown in
Decreasing (increasing) L increases (decreases) the rate at which i L responds to a load dump, as shown in Figure  a load dump ( Figure 14). Note that increasing (decreasing) C O also increases (decreases) the delay time between the load step and the onset of bypass threshold voltage ΔV BP (t d ) (Figure 7), which is why the onset of i L rising shifts with C O .
Although transient-response performance for the proposed dual-mode scheme improves with decreasing L, the same is not true for the single-mode converter whose i L response time is limited by the bandwidth of the loop, not L's slew rate. As a result, as illustrated in Figure 15, the percentage improvement that the dual-mode enjoys over its single-mode counterpart increases with decreasing L: 6-and 1.43-fold improvement at 1 μH-36 μF and 30 μH-36 μF, respectively. Increasing C O decreases v O 's transient droop in both converter cases, except that bypass threshold voltage ΔV BP effectively limits the extent to which a larger C O decreases Δv O in the proposed scheme. In the limit, increasing C O to such an extent that Δv O is less than ΔV BP would prevent the bypass mode from ever engaging. As a result, the performance improvement in Δv O is lower between the  Figures 16 and 17 illustrate how the proposed dual-mode ΣΔ bypass boost converter transitions from steady state to bypass mode and back in response to positive and negative 0.1-0.6A load dumps with an LC combination of 15 μH and 53 μF. As designed, the bypass mode Advances in Power Electronics 9 ripple is larger at ±70 mV (±(H V /2)·(R 1 + R 2 )/(R 2 A DV ) ≈ ±140 mV/2) or ±1.4% than the steady-state counterpart, which is at ±15 mV or ±0.3%. During a positive load dump (Figure 16), when i O suddenly rises, a load-induced drop in v O exceeding the ΔV BP limit engages the bypass mode and increases i L to 2.5 A (I PK ) in one switching cycle of S M . As determined by offset V I.OS , the circuit then takes approximately 2.5 ms to gradually decrease i L back to its new target of roughly 1.3A, at which point S A stops switching and the converter is back in steady state. During a negative load dump (Figure 17), i L is automatically above its target and S A consequently starts diverting some of i L back to V IN almost immediately, until 2.5 ms later, when i L drops to its new target.

Mode Transition.
The main drawbacks of the auxiliary bypass path are the silicon real estate, power, and switching noise associated with power switch S A . The latter two shortcomings, however, are more often than not inconsequential because they only occur during transient events, which are typically sporadic, short, and seldom occur without significantly affecting the steady-state power efficiency ( Figure 18). The prominent disadvantage of the proposed solution is therefore additional silicon real estate for S A because it carries substantial current. The transient-performance benefits of S A and the bypass path that drives it, however, offset this cost.

Conclusion
A dual-mode ΣΔ bypass boost dc-dc controller 0.5 μm CMOS IC that is stable for an R ESR LC filter range of 0-50 mΩ, 1-30 μH, and 1-350 μF and responds to positive and negative load dumps in one switching cycle has been proposed, designed, fabricated, and evaluated. The driving feature of the foregoing solution is a robust on-chip (i.e., smooth transitioning) ΣΔ bypass path that responds only during transient load dumps. While the converter increases inductor current i L in one switching cycle in response to a sudden rise in load current i O and uses it to quickly slew output capacitor C O back to its target, it also limits how much of i L flows to C O in the case of a negative load dump, when i O drops, limiting the total transient variation of output voltage v O and therefore improving accuracy performance. The transient-response benefits of the proposed scheme, as compared to state-of-the-art single-mode ΣΔ converters, are the highest at low values of L (e.g., 6x at 1 μH and 1.41x or 40% improvement at 30 μH) because L limits how fast i L rises and falls to its targets. The main drawback of the proposed technique is the additional silicon real estate required for auxiliary power switch S A , which is partially (and often completely) offset by its improved accuracy performance. In summary, the proposed dual-mode ΣΔ bypass boost converter is fast, widely LC compliant (robust), and easily implementable.