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A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.

The SAR ADC is widely used in many communication systems, such as ultra-wideband (UWB) and wireless sensor networks which require low-to-medium-resolution converters with low power consumption. Traditional SAR ADCs are difficult to be applied in high-speed design; however the improvement of technologies and design methods have allowed the implementation of high-speed, low-power SAR ADCs that become consequently more attractive for a wide variety of applications [

The power dissipation in an SAR converter is dominated by the reference ladder of the DAC capacitor array. Recently, a capacitor splitting technique has been presented, which was proven to use 31% less power from the reference voltage and achieve better DNL than the binary-weighted capacitor (BWC) array. The total power consumption of a 5 b binary-weighted split capacitor (BWSC) array is 6 mW which does not take into account the power from the reference ladder [

This paper presents a novel structure of a split capacitor array for optimization of the power efficiency and the speed of SAR ADCs. Due to the series combination of the split capacitor array both small capacitor ratios and power-efficient charge recycling in the DAC capacitor array can be achieved, leading to fast DAC settling time and low power dissipation in the SAR ADC. The parasitic effects, the position of the attenuation capacitor, as well as the linearity performance (INL and DNL) of the proposed structure will be theoretically discussed and behavioral simulations will be performed. Different from the BWSC array, which only achieves better DNL (but not INL) than the BWC array, the proposed capacitor array structure can have both better INL and DNL than the series capacitor (SC) array. The design and simulations of an 8 b 180-MS/s SAR ADC in 1.2-V supply voltage are presented in 90 nm CMOS exhibiting a Signal-to-Noise-and-Distortion Ratio (SNDR) of 48 dB, with a total power consumption of 14 mW which demonstrates the feasibility of the proposed structure.

The architecture of an SAR ADC is shown in Figure

Simplified block diagram of an SAR ADC architecture.

The major limitation on the speed of the SA converter is often related with the RC time constants of the capacitor array, reference ladder, and switches. For a BWC array the size of capacitors rises exponentially with the resolution in number of bits, which causes large power and RC settling time, thus limiting the speed of the overall SAR ADC. To solve this problem, Figure

(a) (

The solution to perform charge-recycling for SC array is different from the BWC array, which just splits the MSB capacitor

In the proposed implementation the series-split capacitor array is designed to achieve charge recycling for the

To analyze the linearity of the SSC and SC arrays, each of the capacitors is modeled as the sum of the nominal capacitance value and the error term, as follows:

Consider the case where all the errors are in the unit capacitors whose values are independent-identically-distributed Gaussian random variables with a variance of

The accuracy of an SAR ADC is dependent on the DAC outputs which are calculated here in the case of no initial charge on the array (

As a result of (

The maximum DNL for the SSC array is expected to occur at the step below the MSB transition [

One potential issue with these two series capacitor array structures (SSC and SC) is the parasitic capacitances

Four behavioral simulations of the SSC and the SC array DAC were performed to verify the previous analysis. The values of the unit and attenuation capacitors used are Gaussian random variables with standard deviation of 1% (

Behavioral simulations comparing the linearity of the SSC and the SC array.

Behavioral simulation of 1000 Monte Carlo SNDR versus the different bits distribution of MSB and LSB arrays.

Behavioral simulation of 1000 Monte Carlo SNDR versus the percentage of the top-plate parasitic capacitance

Behavioral simulation of 1000 Monte Carlo SNDR versus the percentage of the top-plate parasitic capacitance

The power consumption of the SAR converter is dominated by the DAC capacitor array, the comparator, and the switches’ drivers. The array’s power is proportional to the sum of the array total capacitance

The power consumptions of the comparator and switch drivers are also proportional to the equivalent input capacitance

A high-speed SAR converter imposes a stringent requirement in the clock generation; for example, an 8 b 180 MS/s SAR ADC requires an internal master clock of over 1.62 GHz. To generate such a high-frequency clock pulse the generator will consume even more power than the ADC itself. Due to the power limitations of the clock generator in a synchronous SA design an asynchronous SAR processing technique [

The dynamic comparator [

Circuit schematic of the dynamic comparator.

To verify the proposed capacitor structure of the capacitive DAC, a 1.2 V, 8 b, 180-MS/s SAR ADC was designed using a 90 nm CMOS process with metal-isolator-metal (MIM) capacitor option. The SAR ADC was implemented in a fully differential architecture, with a full scale differential input range of 1.2

Figure

Performance Summary of the SAR ADC.

Technology | 90-nm CMOS with MIM |
---|---|

Resolution | 8 bit |

Sampling Rate | 180 MS/s |

Supply Voltage | 1.2 V |

Full Scale Analog Input | 1.2 Vpp differential |

SNDR (@ | 48 dB |

SFDR (@ | 58 dB |

ENOB (@ | 7.7 bit |

FOM | 0.37 pJ/conversion step |

DNL | |

INL | |

Power Consumption | |

Analog | 9.4 mW |

Digital | 2.3 mW |

Reference ladder | 2.3 mW |

Total | 14 mW |

Simulated FFT spectrum of the ADC.

30-times Monte Carlo simulation of SNDR from the 8 b SAR.

Simulated linearity: (a) DNL and (b) INL.

Simulated SNDR versus power consumption from the reference ladder for series-split (SSC) and binary-weighted split-capacitor array (BWSC).

A novel series-split capacitive DAC technique has been proposed which can both implement an efficient charge recycling SAR operation and achieve a small input capacitance. The reduction of the maximum ratio and sum of the total capacitance can lead to area savings and power efficiency, which allow the SAR converter to work at high speed while meeting a low power consumption requirement. Theoretical analysis and behavioral simulations of the linearity performance demonstrate that the proposed SSC structure can have a better INL and DNL than the traditional SC array structure. Simulation results of a 1.2 V, 8 b, 180-MS/s SAR ADC were presented exhibiting an SNDR of 48 dB at a 76 MHz input with the total power consumption of 14 mW that certifies the power efficiency of the novel circuit structure.

This work was financially supported by research grants from the University of Macau and FDCT with Ref nos. RG-UL/07-08S/Y1/MR01/FST and FDCT/009/2007/A1.