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This paper presents the formation of the parasitic components that exist in the RF MOSFET structure during its high-frequency operation. The parasitic components are extracted from the transistor's S-parameter measurement, and its geometry dependence is studied with respect to its layout structure. Physical geometry equations are proposed to represent these parasitic components, and by implementing them into the RF model, a scalable RFCMOS model, that is, valid up to 49.85 GHz is demonstrated. A new verification technique is proposed to verify the quality of the developed scalable RFCMOS model. The proposed technique can shorten the verification time of the scalable RFCMOS model and ensure that the coded scalable model file is error-free and thus more reliable to use.

The relentless scaling down of CMOS technologies has greatly improved the RF performance of MOSFET. It has been reported that for a technology node of 90 nm, high

Most of the RF models developed today are based on the macromodelling approach. In this approach, subcircuit components are added to the transistor’s core model to model the RF parasitic of MOSFET structure [

In this paper, the geometry dependencies of the RF subcircuit components were studied, and the formulation of these RF components was done based on their physical effects and the geometry of the layout structure. The scalable transistor’s RF characteristics with respect to the layout geometry, biasing, and frequency will be demonstrated with good accuracy between the measured and simulated results. Presently, there is no standard technique proposed for quantifying the quality of a developed scalable RF model. Hence, a new technique is proposed in this paper to help modelling engineers to verify and check the developed scalable RF model for their scalability and accuracy. By utilizing this proposed technique, the model geometry scalability with respect to the transistor’s unit width (

Section

Figure

RF equivalent subcircuit model.

The resistance

The capacitances

Figure

Simplified RF NMOS layout.

In order to extract physical subcircuit components in the macromodel, all the physical layers and their geometry that are used to form the structure of the transistor must be known. The extraction technique used to extract the subcircuit components values is as shown in [

Figure

Simplified polysilicon gate structure and its distributed parasitic resistances.

The polysilicon gate extension

Figure

Extracted and calculated

The resistances

Source and drain metal structure.

Figure

Extracted and calculated (a)

The components ^{2}

Gate-to-substrate capacitance and resistance structure.

Figure

Extracted and calculated (a)

Based on the layout structure in Figure

The capacitance

Gate-to-source and gate-to-drain capacitance structures.

As the dielectric separation distance between the metal 3 (drain) and metal 1 (gate) is larger than the case of metal 2 (gate) and metal 1 (source), it is expected that

Figure

Extracted and calculated (a)

Drain-to-Source capacitance structure (a) and extracted and calculated

In Figure

By using the cross-section view of A-A′ in Figure

Substrate resistances network.

In Figure

Extracted and calculated (a)

The devices under test (DUT) are thin gate NMOSs with fixed

In order to demonstrate the scalability of the RF model, measured and simulated DC, Y-parameters, and

Measured and simulated results for NMOS transistor with

Measured and simulated results for NMOS transistor with

Measured and simulated results for NMOS transistor with

Measured and simulated results for NMOS transistor with

Measured and simulated results for NMOS transistor with

In a scalable RFCMOS model, there are many different variables that determined the scalability of the RF model. It becomes very tedious to verify and monitor the model accuracy further so that the developed model, file has to be scalable for a certain range of geometry, biasing and frequency variables. Hence, a new verification technique is proposed in this paper. This proposed verification technique is crucial to both the modelling engineers and the model file end users as it helps them to monitor the quality of the developed model and at the same time, the model file can be checked for any errors in the coded geometry equations of the parasitic subcircuit components. Furthermore, by using this proposed technique, the amount of verification time required to check the developed model file is reduced, and thus reducing the overall model development time.

Figure

Model accuracy for NMOSFETs with different

Figure

Model continuity for

In this proposed technique, the model accuracy and continuity plots are generated to monitor the device geometry, biasing, and frequency variables of the RF model. From these two types of plots, the quality of the developed model and the coded model file will be inspected, and the final verified model file will be error-free and reliable to use.

The proposed model accuracy and continuity plots can also be used as one of the model acceptance criteria, whereby its accuracy and continuity can be checked before accepting and using the developed RF model file.

In this paper, the physical formation of the subcircuit parasitic is discussed with respect to its layout structure. The scaling effect of the device geometry is accounted for in the proposed scalable equations for each of the parasitic components. By implementing the proposed scalable equations for the parasitic components into the conventional subcircuit RF model, a scalable RFCMOS subcircuit model can be generated and shown to be valid up to 49.85 GHz. By using the proposed verification technique, the time required to verify a scalable RFCMOS model can be reduced greatly, and the verification step can also ensure that the developed model is error-free, and therefore, it is more robust and reliable to use. Although the scalable RFCMOS model can accurately predict the DC and RF characteristics of the transistor it will still require being able to predict its high-frequency noise. Hence, the scalable RFCMOS model will form the base of the RF transistor modelling so that the study of the scalable high-frequency noise modelling can be embarked on to achieve a fully scalable RFCMOS model.

The authors would like to thank K. Takeshita, M. Yano, M. Abe, A. Nakamura, A. Kuranouchi, and S. Tonegawa from Sony for their helpful discussions and valuable inputs.