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Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like “don't care bit filling” and “reordering” which do not require any modification in internal structure and do not demand use of any test development tool can be used for SoC-containing IP cores with hidden structure. The proposed “Weighted Transition Based Reordering-Columnwise Bit Filling-Difference Vector (WTR-CBF-DV)” is a modification to earlier proposed “Hamming Distance based Reordering—Columnwise Bit Filling and Difference vector.” This new method aims not only at very high compression but also aims at shift in test power reduction without any significant on-chip area overhead. The experiment results on ISCAS89 benchmark circuits show that the test data compression ratio has significantly improved for each case. It is also noteworthy that, in most of the case, this scheme does not involve any extra silicon area overhead compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. As application of this scheme increases run length of zeroes in test set, as a result, the number of transitions during scan shifting is reduced. This may lower scan power. The proposed scheme can be easily integrated into the existing industrial flow.

The testing cost and testing power are the two well-known issues of current generation IC testing [

The test cost is directly related to test data volume and hence test data transfer time [

So it can be inferred that the test data compression and switching reduction in context of hidden structure of IP core is the current need for SoC testing.

In literature, there are many test data compression techniques like linear decompression-based, broadcast scan-based, and code-based techniques. Considering to suitability to IP core-based SoC, code-based test data compression scheme is more appropriate. From the various code-based test data compression schemes like dictionary codes, constructive codes, statistical codes, and run length-based codes, the run length-based codes can be more suitable to IP cores because of its simple on-chip decoder and better compression capacity. The do not care bit filling methods and test vector reordering further enhance the test data compression.

The switching activity reduction technique described in literature can be broadly classified in three categories: (1) techniques for built-in self-test, (2) techniques applied as design-for-test, and (3) techniques for external testing. Considering the suitability to IP cores, the techniques for external testing can be further explored. Out of various switching reduction techniques for external testing like low-power ATPG, input control, reordering, and do not care bit filling, the do not care bit filling and reordering are applicable for hidden structure of IP core.

To improve the compression ratio and to reduce the switching in the most famous run length-based data compression method, in this paper, a new scheme based on three techniques: Hamming distance and weighted transition-based reordering (WTR), columnwise bit filling (CBF), and difference vector (DV) is proposed. This scheme is applied to various test set prior to apply a variety of run based codes, and it gives better result in each of the case. The experiment results show that the test data compression ratio is significantly improved. Moreover, this scheme does not require any on-chip silicon area overhead compared to base run length code with which it is used. With the help of weighted transition-based reordering, the total number of transition during scan-in is also reduced. This method may reduce the overall scan power requirement during testing. Further, the proposed scheme can be easily integrated into the existing industrial flow.

The paper is organized as follows: the background for bit filling methods and test vector reordering used for test data compression and test power reduction is covered in Section

In 1998, a scheme based on run-length codes that encoded runs of 0 s using fixed-length code words [

Instead of simply filling all do not care bits with 0 s, if the do not care bits are filled considering the type of run used in particular compression scheme, the better compression can be achieved [

Stuck at fault-based test patterns can be reordered without any loss of fault coverage. In literature, a number of test vector reordering techniques are proposed for test data compression. The run-based reordering approach [

For the reduction of switching activity in terms of number of transitions during scan operations, the do not care bit filling and reordering techniques are widely used.

The greedy algorithm based reordering process using the minimum Hamming distance between them to reduce the scan power [

An automatic test pattern generation (ATPG) scheme for low-power launch-off-capture (LOC) transition test based on do not care bit filling is proposed in [

The earlier proposed Hamming distance-based reordering, column-wise bit filling, and difference vector (HDR-CBF-DV) are taken as the basic scheme for the proposed method. This section includes the introduction to (HDR-CBF-DV) and the proposed modifications.

Before continuing the further explanation, the following two terms need to be defined.

The Hamming distance between two scan vectors is equal to the number of corresponding incompatible bits. This definition is similar to Hamming distance with extension of do not-care bits. For example, given two vectors

For a given test data set containing m vectors with

If we take each test pattern as a vertex in a complete undirected graph

In [

In WTR-CBF-DV, if there are more than one test vectors with minimum number of do not care bits, each will be evaluated for its weighted transitions, and the vector with minimum weighted transition will be selected as the first test vector of the reordered test set. Further in earlier method, the first vector is kept unfilled until all the test vectors are reordered, but, in the proposed scheme, the selected first vector is MT filled before continuing reordering to make the overall testing and selection of remaining test vectors power aware.

For reordering of the remaining test patterns in [

During the reordering process for various circuits, it is found that generally the test set contains more than one test vectors with same Hamming distance. This happens because of the structural behavior of faults. This tie should be broken in favor of power reduction. So in the proposed scheme, while selecting the next vector of the reordered test set, if there are more than one vector with the same Hamming distance from the last selected vector of reordered set, then the weighted transition will be taken into consideration. All these equidistance vectors will be applied columnwise bit filling (explained in Section

The next step is to take the difference vector of two consecutive vectors in reordered set. This will further increase the numbers of zeroes and hence data compression. Any run length code can be used to compress the difference vector sequence

For the proposed method, the test data will be first preprocessed by WTR-CBF-DV scheme, and then the frequency-directed run length code (FDR) [

Frequency directed run length code.

Run length | Group prefix | Tail | Code word | |
---|---|---|---|---|

0 | 1 | 0 | 0 | 00 |

1 | 1 | 01 | ||

2 | 2 | 10 | 00 | 1000 |

3 | 01 | 1001 | ||

4 | 10 | 1010 | ||

5 | 11 | 1011 | ||

6 | 3 | 110 | 000 | 110000 |

7 | 001 | 110001 | ||

- | - - - | - - | - - - - - - |

Example of frequency-directed run length coding.

Consider a digital circuit with

Find test vector with minimum number of do not care bits in the given test set.

If there are more than one vector with minimum do not care bits, then

apply MT fill to each vector,

calculate weighted transition for each vector,

select the MT-filled vector with minimum WT as first vector of reordered set.

Find the Hamming distance of remaining each vectors from the first vector of reordered set.

Select the vector with minimum Hamming distance as next vector.

If there are more than one vector with minimum Hamming distance, then

apply columnwise bit fill to each vector, that is, replace the do not care bit of the vector with the same position bit value of last selected vector,

calculate weighted transition for each vector, and

select the columnwise bit filled vector with minimum WT as next vector of reordered set.

Repeat step (6) until all the vectors are reordered.

Apply difference vector mechanism.

First vector of reordered set is kept unchanged.

From the second vector onward, if the same position bits in last vector and current vector are same, replace the bit with 0 else 1.

Apply frequency-directed run length code.

Considering the following test data, for example,

test vector 1 X 1 0 0 X X 0 1 X 0 0 X 1 1 1 1 X 0 X 0 X 1 0 1 0 X X 1 0 1 1 0 X 0 0 X X X 0 1 0 0 X X 0 X X 1 0 X X X 0 X X 1 0 1 X 1 X 1 X 1 0 X 0 0 X 1 1 1 1 0 X 0 0 X X X X 0 0

In the above test data, vector

test vector 1 0 1 1 0 0 0 0 0 0 0 0 1 0

its corresponding weighted transition as per (

After placing the

test vectors after first vector reordered 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 X 0 X 0 X 0 0 X X 1 X 1 0 X X 0 X 0 0 X X X X X 0 X X X 0 X X 1 0 1 X X X 0 X 0 X 1 1 1 0 X 0 0 X X X X 0

Now the Hamming distance of remaining each test vector

Partially reordered test vectors 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 X 1 0 0 X X 0 1 X 0 0 X 1 0 X X 0 X X 1 0 X X X 0 X X 1 0 1 X 1 X 1 X 1 0 X 0 0 X 1 1 1 X 0 X 0 X 1 0 1 0 X X

Now the Hamming distance of

Partially reordered test vectors 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 X X 0 X X 1 0 X X X 0 X X 1 0 1 X 1 X 1 X 1 0 X 0 0 X 1 X 1 0 0 X X 0 1 X 0 0 X 1

Now the remaining all three

Test vector 1 1 1 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0

Applying (

Test vector 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 1 0 0 0

Test vector 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 1

The same way the possible weighted transitions for

reordered test vectors 1 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1

The next step is to take the difference vector of two consecutive vectors in reordered set to increase the numbers of zeroes and hence data compression. The difference vector set is as shown below:

difference test vectors 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0

The difference vector set applied the frequency directed run length coding as described in Section

In Table

Comparison of test data processing methods.

MT Fill | Diff. Vector | HDR-CBF-DV | WTR-CBF-DV | |
---|---|---|---|---|

% Compression | −2.381 | 7.1429 | 16.6667 | 16.6667 |

Peak power | 38 | 81 | 82 | 82 |

Average power | 23.8333 | 36.8333 | 42.1667 | 38.6667 |

For the WTR-CBF-DV, the working model is developed using MATLAB7.0 language and then for extensive experimental work, the C language is used. The experiments are conducted on a workstation with an Intel 2 GHz Core2Duo CPU T5750 with 3 GB of memory. The six largest ISCAS89 full-scan circuits have been considered for this experiment. For all ISCAS89 circuits, the test sets (with do not care) obtained from the Mintest ATPG program are used. Tables

Do not care bits are MT filled, but no reordering is applied.

Do not care bits are filled on the basis of run type, but no reordering is applied.

Do not care bits are filled with 0 s, and difference vector is applied [

HDR-CBF-DV applied.

2-D reordering is applied.

WTR-CBF-DV applied.

Comparison of % compression for various test data processing methods.

ISCAS circuit | Minimum transition fill | 0 Filling + XOR [ | Run based bit fill maximum limit | HDR-CBF-DV | 2-D Reordering | WTR-CBF-DV |
---|---|---|---|---|---|---|

s5378 | −12.31 | 48.02 | 52.36 | 62.33 | 59.66 | 62.15 |

s9234 | −20.67 | 43.59 | 47.80 | 61.06 | 61.35 | 63.31 |

s13207 | 6.16 | 81.30 | 83.65 | 87.47 | 88.22 | 88.04 |

s15850 | −17.91 | 66.22 | 68.18 | 72.84 | 73.96 | 73.38 |

s38417 | −20.39 | 43.26 | 54.5 | 66.18 | 65.13 | 66.38 |

s38584 | −8.90 | 60.91 | 62.49 | 64.79 | 66.08 | 65.21 |

Comparison of average power for various test data processing methods.

ISCAS circuit | Minimum transition fill | 0 Filling + XOR [ | Run based bit fill maximum limit | HDR-CBF-DV | 2-D Reordering | WTR-CBF-DV |
---|---|---|---|---|---|---|

s5378 | 3433 | 3526 | 3526 | 11133 | 7934 | 10344 |

s9234 | 3958 | 4022 | 4022 | 14382 | 13329 | 13492 |

s13207 | 7735 | 7887 | 7887 | 113890 | 78856 | 103400 |

s15850 | 13514 | 13659 | 13659 | 82421 | 71015 | 64275 |

s38417 | 117540 | 118080 | 118080 | 452860 | 486000 | 443030 |

s38584 | 85656 | 86305 | 86305 | 410240 | 423260 | 329110 |

Comparison of peak power for various test data processing methods.

ISCAS circuit | Minimum transition fill | 0 Filling + XOR [ | Run based bit fill maximum limit | HDR-CBF-DV | 2-D Reordering | WTR-CBF-DV |
---|---|---|---|---|---|---|

s5378 | 11519 | 12085 | 12085 | 13327 | 11769 | 12822 |

s9234 | 14092 | 15395 | 15395 | 17828 | 16106 | 17169 |

s13207 | 94879 | 110129 | 110129 | 128638 | 95541 | 125392 |

s15850 | 70875 | 84360 | 84360 | 96084 | 98903 | 96452 |

s38417 | 437884 | 514716 | 514716 | 644262 | 633561 | 660096 |

s38584 | 481158 | 530464 | 530464 | 550037 | 532809 | 551602 |

Any of test data compression methods needs an on-chip decompressor, which loads compressed data from automatic test equipment (ATE) and restores the original test data. The decompressed test data will be transmitted to design under test. The WTR-CBF-DV is a test data processing method applied in conjunction with FDR coding. The same FDR decoder described in [

On-chip decoder for WTR-CBF-DV.

In this paper, a scheme comprising of Hamming distance and weighted transition-based reordering (WTR), columnwise bit filling (CBF), and difference vector (DV) for test data compression is proposed. This scheme is applied to preprocess the test data before applying the FDR compression method. The proposed test data processing scheme improves the % compression compared to earlier methods described in literature. Moreover, this method increases the compression beyond the limit of maximum possible compression for run based bit filled data. The peak power and average power is a tradeoff with % compression, but still it is controlled using weighted transition-based reordering. The proposed scheme demands no extra on-chip area overhead compared to earlier methods in literature.