Temperature Dependence of GaN HEMT Small Signal Parameters

This study presents the temperature dependence of small signal parameters of GaN/SiC HEMTs across the 0–150◦C range. The changes with temperature for transconductance (gm), output impedance (Cds and Rds), feedback capacitance (Cdg), input capacitance (Cgs), and gate resistance (Rg) are measured. The variations with temperature are established for gm, Cds, Rds, Cdg, Cgs, and Rg in the GaN technology. This information is useful for MMIC designs.


Introduction
Devices based on wide bandgap materials (such as GaN, SiC) promise much higher power densities and potential for higher temperature operation than GaAs, Si, and SiGe devices [1][2][3]. The reliability and performance of HEMTs and MMICs depend critically on the device operating channel temperature [4,5]. Previous studies [6][7][8][9][10][11] have focused on various effects with temperature. However, the referenced temperature was the chuck (or base plate) temperature. This study presents characterization and comparison of two current GaN/SiC devices from different foundries across temperature where the temperature is reference to the channel reference.

Measured Results
To quantize the effect of temperature on the performance of GaN/SiC device, two state-of-the-art AlGaN/GaN HEMT devices were characterized at −25, 25, 75, and 125 • C base plate (on-wafer chuck). At each temperature, S-parameters are measured at V d = 20 V and a fixed drain current (equal to 25% of the room temperature I dss ) and the small signal extracted. The dissipated DC power is fixed, and hence the channel temperature to the chuck temperature is constant. For example, in the first device the temperature difference between the channel and the chuck was 26 • C (calculated from finite element simulation of the structure), temperature contours shown in Figure 1. In both devices, the gate length (L g ) for the HEMT was about 0.25 µm and the gate width was 2 × 100 µm. A standard equivalent circuit is used to match the measurements, see Figure 2. The model used includes a source inductance L s and resistance R s to model the via holes to ground. In the current case, a via hole structure was measured independently in order to find L s and R s . Additionally, the input and output feeding structures (Figure 3), were constructed on full wave analysis simulator (EM Sight from Microwave Office Suite) and simulated. The structures were used to de-embed the S-parameters. This is a critical step to separate the intrinsic device behavior from the extrinsic-layout-dependent behavior. In the optimization, the S-parameters are normalized to give equal-weight real and imaginary parts as well to all the parameters (S 11 , S 21 , S 12 , and S 22 ). Upon de-embedding and optimization of the S parameters against the layout circuit, several important points are noted for both devices. First, the optimization is very robust and always arrives at the same values for various R s and L s . Second, the match between the measurement and model is very close, at all frequencies and temperatures, see Figure 4. Third, the optimized values for the parasitic components L g , L d , C ds , and R d are zero, indicating that the feeding structures account for them completely. The only exception is R g where the gate resistance was not fully included in the input matching structure because the 2 International Journal of Microwave Science and Technology  resistance is sensitive to the exact gate dimension and shape (T-gate, Mushroom gate, etc.) information which was not available.
For each device type, two identical transistors were measured to check for consistency of the results. Figures 5, 6, 7, 8, and 9 show the temperature dependence of C gs , C dg , R g , R ds , and g m , respectively. In all cases, the values are normalized to 1 mm gate periphery. For example, in Figure 4, a C gs value of 1 pF corresponds to 1 pF/mm, and, for a 2 × 100 µm device, C gs would be 0.2 pF. Figure 10 shows the saturation current (I dss ).

Discussion and Analysis
The measured results contain a number of findings. In particular, the following may be noted.
(1) The transconductance g m decreases with temperature, as expected. The mean square slope of g m versus T is −0.16%/ • C and −0.25%/ • C for the two devices.
(2) The gate resistance R g with temperature, as expected, is at a slope of 0.27%/ • C and 0.22%/ • C for the two devices.
(3) The change in input capacitance C gs with temperature is −0.12%/ • C and −0.34%/ • C for the two devices. The decrease in capacitance with temperature could be due to decrease in sheet charge or charge confinement with temperature. It merits further investigation. (4) The change in feedback capacitance C dg with temperature is 0.11%/ • C and 0.14%/ • C for the two devices. An increase in C dg is generally detrimental to achieving high performance as it decreases gain and efficiency. Reduced charge confinement is expected to increase the feedback capacitance, which may indicate a link between the feedback capacitance C dg increase and the input capacitance C gs decrease. Further studies are required.
(5) The output resistance R ds is a very critical parameter as it directly influences power added efficiency, and output power. A small R ds results in more RF power dissipation inside the transistor. Hence, the increase in R ds with temperature should reduce the decline of efficiency and P out with temperature. It increases with T at 0.3%/ • C and almost 0%/ • C for the two devices.
(6) In each case, a linear fit (using least square error) is shown. This should prove valuable in device modeling as most models (Angelov, EEHEMT, Curtice, etc.) allow temperature coefficients of various components and there is a general lack of experimental values.

Conclusion
From the preceding measurements, one may conclude that GaN HEMT devices experience higher parasitic, greater feedback capacitance, and lower gains with temperature. However, the degradation observed is less than (or equal to) GaAs degradation with temperature. Additionally, if the input matching network (which compensates for C gs ) and the output matching network (which compensates for C ds and C dg ) can tolerate 10-15% variation in the reactance value, then they will work over 100 • C range.