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An artificial cell is comprised of the most basic elements in a hierarchical system, that has minimal functionality, but general enough to obey the rules of “artificial life.” The ability to replicate, organize hierarchy, and generalize within an environment is some of the properties of an artificial cell. We present a hardware artificial cell having the properties of generalization ability, the ability of self-organization, and the reproducibility. The cells are used in parallel hardware architecture for implementing the real-time 2D image convolution operation. The proposed hardware design is implemented on FPGA and tested on images. We report improved processing speeds and demonstrate its usefulness in an image filtering application.

Last two decades of study on artificial life revolve around the problem of understanding the organizational principles of life by treating “cells” as the basic blocks of information processing and transmission [

Biological cells can be considered as the basic modules of physical life in embryonic systems and are an inspiration to the conceptual creation of artificial cellular systems. Ideally, the conceptual artificial cells can be organized hierarchically having the properties of the near perfect self-organization, self-reproduction (multiplying), and fault tolerance (cicatrization). These properties often result in a network of huge number of cells. Such bioinspired networks of artificial cells can be organized to perform a function or a set of functions. The implementation of artificial cells in hardware [

In this paper, we propose an artificial cell that carries basic genetic features (basic arithmetic and logical operations) having the properties of generalization ability, the ability of self-organization, and reproducibility. The artificial cells are used to create cellular system networks that implement 2D image convolution, which represent a general and complex image processing operation having several practical machine vision applications.

In developing a robust digital logic system for application such as image processing, the traditional fault reduction and generalisation methodologies seem to be inefficient and expensive [

The research methodology of this paper can be summarised in four stages.

The cell architecture was designed in VHDL and tested in the typical FPGA framework. The architectural concepts were adapted from the idea of artificial cell and the genotype definition of the cell formed in terms of arithmetic and logical operations.

Several test cases are designed and the performance of the cell analyzed using a standard FPGA system simulator.

After the functionality of the cell is verified, the architecture is implemented to perform the image convolution operation.

The performance of the convolution operation implemented with the proposed architecture is compared with an ALU based benchmark algorithmic implementation done in MATLAB.

In image processing, convolution is an essential kernel-based operator used for (1) intensity averaging to remove signal noise gained from erroneous sensing, (2) edge or gradient detection, (3) local range detection, and (4) local standard deviation calculations [

Convolution architecture is constructed from cells that process in parallel to solve mathematical and logical functions. The cell computes arithmetic and logic operations in a synchronous and parallel manner. The architecture is tested on different picture sizes in a pixel-dedicated fashion and a sequential fashion. In the pixel-dedicated fashion, the cell architecture is applied to every pixel at a time to yield a true parallel convolution image processor. In contrast, in the sequential fashion, the cell architecture is applied to individual pixels at an expense of one clock cycle for every pixel. This section will show the cell design, the architectural design, and the test bench design for the sequential setup.

Figure

Operation code inputs.

3 bit input code | Basic operations |
---|---|

0000 | Rest |

0001 | Addition |

0010 | Subtraction |

0011 | Accumulation |

0100 | Multiplication |

0101 | Division |

1000 | AND |

1001 | OR |

1010 | XOR |

1011 | NAND |

1100 | NOR |

1101 | XNOR |

RTL block diagram of the proposed artificial cell.

The cell is based on the arithmetic and the logical blocks that perform the defined arithmetic and logical genome. The arithmetic block performs the simplest arithmetic operations like addition, subtraction, accumulations, multiplication, and division. The status bit is enabled high when the cell processes and completes the requested operation, resulting in a 32 bit cell output. The status bit is essential for communicating with neighboring cells if needed, for higher hierarchical level network implementations.

The cell is tested with different decimal values to verify the varieties of different outputs like signed, unsigned, and float decimal values. Figure

Arithmetic test conditions and cell output.

Time | Operation (binary) | Function | In 1 | In 2 | Output |
---|---|---|---|---|---|

0 ns | 0001 | Addition | 1327 | 338 | 1710 |

1 ns | 0010 | Subtraction | 84 | 3971 | −3888 |

2 ns | 0100 | Accumulation | 84 | 0 | 85 |

3 ns | 0100 | Multiplication | 3419 | 363 | 1241097 |

4 ns | 0100 | Division | 3419 | 363 | 9.419 |

5 ns | 0000 | Reset | 0 | 0 | 0 |

Timing diagrams representing outputs from “arithmetic operation” of the artificial cell.

Figure

Logic test conditions and cell output.

Time | Operation (binary) | Function | In 1 | In 2 | Output |
---|---|---|---|---|---|

0 ns | 1000 | AND | 10101000 | ||

1 ns | 1001 | OR | 10111110 | ||

2 ns | 1010 | XOR | 00010110 | ||

3 ns | 1011 | NAND | 10101010 | 10111100 | 01010111 |

4 ns | 1100 | NOR | 01000001 | ||

5 ns | 1101 | XNOR | 11101001 | ||

6.5 ns | 0000 | Reset | 00000000 |

Timing diagrams representing outputs from “logic operation” of the artificial cell.

This section describes the overall design of the proposed artificial cell-based convolution architecture for image processing. Convolution in image processing is a linear operator over a matrix (image) by another one which is called “kernel.” A

The hierarchical cell architecture for 2D convolution operator.

Figure

Convolution result of the convolution architecture performed on a single pixel.

An example of the input image (a) applied to the convolution processor. The image (b) shows the output of the convolution processor for the applied input image (b). Note that the image (b) is normalized for display purpose.

An artificial cell-based 2D convolution processor is designed with a speed of 2 GHz without any negative slack. Figure

Function block diagram of ALU-based convolution.

A comparison of convolution operator execution times of ALU design with that of proposed artificial-cell-based design.

The design is composed of a clock generator that generates a 1 ns signal and a 100 ns signal. The data collector is synchronized to read 1 pixel every 1 ns. The data collector provides

Figure

Inspired from the conceptual framework and properties of a cell, we form a generic artificial cell useful for implementing important machine vision function such as 2D image convolution. Using the concepts of cell hierarchy and multiplicity, we demonstrated the use of the proposed cell architecture in a practical application of image convolution. The proposed implementation of convolution operation when used in real time image processing system show lower time complexity than conventional ALU-based convolution implementation. Further, the parallel nature of the proposed architecture ensures the ease of scaling and robustness in functional implementation. Since convolution is a general operator that is used in almost all real-time digital image processing systems, the proposed system can be used to implement intelligent image processing cameras. The general idea of the artificial cell can be further exploited in designing high-speed object matching, tracking, image filtering, and recognition systems. In addition, the presented research can be extended to create more generalist cell architectures that can simulate and model complex processes such as protein-protein interactions, cell signaling, and high dimensional data processing.