The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.
Binary addition is one of the most primitive and most commonly used applications in computer arithmetic. A large variety of algorithms and implementations have been proposed for binary addition [
Consider the
Schematic of bit generate circuit using CMOS and transmission design style.
These are then utilized to compute the final sum and carry bits, in the last stage as follows:
Block diagram of grey cell and black cell.
In this paper, mathematical analysis is given for Ling adders. Similar analysis can be given for all other adders as well.
The Brent-Kung tree computes prefixes for 2-bit groups. These are used to find prefixes for 4-bit groups, which in turn are used to find prefixes for 8-bit groups, and so forth. The prefixes then fan back down to compute the carries-in to each bit. The tree requires
The
The
The main difference between Kogge-Stone adders and other adders is its high performance. It calculates carries corresponding to every bit with the help of group generate and group propagate. In this adder the logic levels are given by
Ling [
Bit generate and propagate in Ling CLA.
Bit generate, propagate, and half-sum bits using transmission gates.
Figure
Figure
Ling generate and propagate in Ling CLA.
Block generate and propagate (Ling carry) using CMOS and transmission gate.
Finally the block generates are used to calculate the final sum along with the bit propagate half-sum bits to calculate the sum as in Figures
Sum in Ling CLA.
Sum block in Ling adder using CMOS and transmission gates.
Adders are extensively used as a part of filters. Lattice filter structures are used in various signal processing applications, and they are internally considered in the present work. The block diagram of third-order lattice filter is shown in Figure
Third-order cascaded IIR lattice filter structure.
For cascaded lattice filter shown in Figure minimum period: 13.058 ns (maximum frequency: 76.579 MHz), minimum input arrival time before clock: 2.680 ns, and maximum output required time after clock: 21.707 ns. minimum period: 11.097 ns (maximum frequency: 90.112 MHz), minimum input arrival time before clock: 2.697 ns, and maximum output required time after clock: 13.476 ns.
Similarly for lattice filter with Kogge-Stone Ling adder the postsynthesis results are as follows:
Hence the clock frequency of any digital filter blocks is found to increase if Kogge-Stone Ling adder is used. This can be used for any digital blocks where operation speed needs to be high.
Schematic is constructed for 8 bit and 32 adders using CMOS and transmission gates as given in Figures
Delay, power and area consumed for different adders: a comparision.
Adder | Number of bits | CMOS logic | Transmission gate logic | ||||
---|---|---|---|---|---|---|---|
Area (no of transistors) | Power in W | Delay in sec | Area (no of transistors) | Power in W | Delay in sec | ||
Kogge-Stone | 8 | 486 | 4.13 m | 432 | 1.8799 m | ||
16 | 1140 | 7.694 m | 1056 | 5.2718 m | |||
32 | 2658 | 13.648 m | 2345 | 10.314 m | |||
Sklansky | 8 | 415 | 17.88 m | 323 | 8.92 m | ||
16 | 1047 | 36.34 m | 763 | 18.73 m | |||
32 | 2199 | 65.13 m | 1659 | 40.2 m | |||
Brent-Kung | 8 | 598 | 0.18 | 470 | 0.13 | ||
16 | 1268 | 0.4 | 1012 | 0.3 | |||
32 | 2494 | 12.5 | 1982 | 0.614 | |||
Han-Carlson | 8 | 440 | 10.81 m | 312 | 1.9178 m | ||
16 | 992 | 13.54 m | 736 | 6.411 m | |||
32 | 2208 | 13.99 m | 1696 | 9.825 m | |||
Ling | 8 | 742 | 0.313 | 530 | 0.139 | ||
16 | 1655 | 0.6 | 1250 | 0.3104 | |||
32 | 3382 | 13.3 m | 2690 | 0.4105 |
Schematic of 16-bit Kogge-Stone adder using transmission gates.
Schematic of 16-bit Brent-Kung adder using transmission gates.
Schematic of 16-bit Sklansky adder using transmission gates.
Schematic of 16-bit Han-Carlson adder using transmission gates.
Schematic of 16-bit Kogge-Stone Ling adder using transmission gates.
Here signed and unsigned magnitude comparator [
(a) Schematic of 16-bit unsigned comparator, (b) Schematic of 16-bit signed comparator.
From the above work, it was seen that the clock frequency for the IIR filter using Ling adder was more than the clock frequency for the same IIR filter using simple ripple adder. The combinational path delay for the Ling adder was found to be 15% lesser than that for the ripple adder. Using transmission gates reduced the area of the adder and hence the comparator built using the adder, as compared to the area consumed when CMOS logic was used for implementation. Using transmission gate logic reduced the delay and power consumption of the adder, and hence the comparator using these adders, as compared to the delay and power consumed when CMOS logic was used for implementation. The power consumed by the comparator using Ling adder is lesser than the power consumed by comparator designed using other normal tree adders.