This paper investigates the numerical issue of a discrete-time induction-motor emulator implementation. The stability analysis of the finite-word-length implementation shows a coupling between required word length and the sample rate. We propose specific guidelines to analyze this coupling and to estimate the required data word length for both signals and coefficients of the model. To respect algorithm requirements, an FPGA-based implementation was used for architecture development. The direct torque control is implemented to verify in real time the AC-motor emulator prototype.
Control algorithms of electrical drives are usually tested by the attachment of electrical motors. Experimental testing requires direct measuring by employing measurement instrumentation and sensors that would be complex, impractical, noise sensitive, and expensive. Traditionally these tests are performed on motor and inverter models under software simulation environments which are, in most cases, non-real-time and unable to exactly replicate real operational conditions.
In order to provide a real-time verification of the implemented control algorithm and increase the realism of simulation, the control algorithm is tested while connected to a real-time emulator for the plant (induction motor and inverter) [
For reasons of cost, simplicity, speeds and memory space, the real-time emulator of the induction motor is performed with the Euler’s shift discretization method and quantized with fixed point format [
The robustness of the discretized algorithm is a critical issue in fixed-point format implementation. It is well known that, stable, closed-loop system may become unstable when the algorithm is implemented using a fixed-point processor due to finite-word-length effects. The fractional part precisions in fixed point are chosen to guarantee a minimum signal-to-noise ratio for finite-word-length quantization effects. The integer part is computed using norms [
In an FPGA implementation, it is possible to use separate fixed-point format for each coefficient and signal in the algorithm. Hence, the use of FPGA allows maintaining a higher computational precision at critical points.
In this paper, authors propose a real-time induction motor emulator designed in fixed point format for an FPGA implementation. The starting point is a continuous-time model. Discrete-time models are derived using the traditional shift form approximation. A study in terms of stability and finite-world-length effects is shown and a design technique for choosing the coefficient and signal bit widths is given [
To demonstrate the accurateness of the real-time induction motor emulator, a particular example is developed: the direct torque control (DTC) of an induction motor [
The paper is organized as follows. The second section reminds the algorithmic study of a discrete-time induction motor model-based shift form approximation. Section
The block diagram of the complete system is outlined in Figure
Block diagram of the DTC technique.
As it can be seen, the DTC algorithm is decomposed in three specific blocks. Transformation block, which is composed by two subalgorithms based on the direct Concordia transformation algorithm for the current and voltage three phases models. Estimation block, which is composed by the calculation subalgorithms of flux command block, which is composed by a look-up table (LUT) corresponding to the switching function of the power inverter.
In order to provide a real-time verification of the implemented control algorithm, the DTC is tested while connected to a real-time emulator for the induction motor and inverter.
The induction machine is a nonlinear high-order system and for this reason complicated models must be used to control it. The dynamic behaviour of the induction motors can be described by a set of differential equations in a rotating reference frame with an angular velocity of
By means of
The purpose of this section is to develop a computationally efficient discrete-time approximation of the continuous motor model operating in real time.
The most used discretization method is based on Forward shift approximation [
Introducing (
The data flow graph (DFG) corresponding to the induction motor model is presented in Figure
The DFG of induction motor model.
The following lines show the different coefficients used for the per unit (PU) DTC algorithm
The base values are determined from the maximal values by using the following equations, where
The solution of the continuous system
And if we consider the solution at the instant
The solution at the instant
Therefore, the matrices that rule the continuous and discrete time systems are, respectively,
The poles of the matrix
In this study, a low power induction motor (1.5 kW) has been considered. The corresponding continuous-time model has four poles for electromagnetic model as illustrated below:
Let us suppose the following quadratic error function:
Therefore, for sampling periods
Discrete-time systems resulting from the shift form approximation are sometime unstable. It is possible, however, to select the sampling rate such that the discrete-time system is always stable when the corresponding continuous-time system is stable. For the shift form realization, the stability domain is located inside the unit circle. Therefore, a
Therefore, the most critical
The locations of poles of the motor for different sampling rate values are shown in Figure
The following methodology is developed for choosing each coefficient and variable bit width.
When the model is implemented in fixed-point format, each coefficient
The integer part position for a coefficient
The fractional part must be determined by the maximum allowable perturbation of the coefficient from its ideal infinite-precision value. This can be achieved by computing the quantized parameter deviation or sensitivity and the stability margin. The angular velocity is selected to be the worst-case value. By means of Figure
Let
Due to the finite-word-length effects, each
Due to the perturbation
As an example, for poles
The quantized pole
Assuming that all coefficients have the same word-length fractional part, then
From inequalities (
For the studied motor, setting
The next step in the fixed-point motor model implementation is to estimate the format for each signal. An incremental methodology is used to determine the appropriate representation for the state variables. As shown in Figure
Incremental methodology for signal representation.
The dynamic range (maximum amplitude) of each signal of the DFG allows identifying their integer range. In practice the maximal current supported by the motor as well as the maximal produced torque and fluxes is known. Therefore, for the per-unit motor model, these dynamic ranges are bounded by 1. Notice that the voltage inputs and the electrical velocity are also normalized. Thus, these dynamic ranges are all bounded by 1:
Now considering internal
Therefore, signals
The integer part word length of all the signals is then estimated by taking the base 2 logarithm of the range bound. Table
Range bounds for the motor model signals.
Signal | Range bound | Integer size |
---|---|---|
|
1 | 1 |
|
1.03 | 2 |
The fractional part word length is estimated by analyzing the signal-to-quantization-noise ratio (SQNR) for each signal [
There are two possible sources of quantization noise in the induction motor emulator implementation, namely: the noise introduced by the limited resolution of a possible control technique, producing an input noise variance the truncation noise which is introduced when products or sums are quantized. This noise propagates through the emulator and appears at outputs.
It is assumed that the quantization noise has the following properties. Each quantization noise source is a stationary white noise process. Each noise source is uncorrelated with all other noise sources and the input of the system. The error resulting from quantization can then be modeled as a random variable uniformly distributed over the appropriate error range. Therefore, the noise variance due to truncation is
where
To investigate the noise propagation, a noise quantization model of the induction motor emulator is developed in Figure
An additive noise model for the truncation and control technique noise through the induction motor model.
The output noise variances can be estimated using the matrix transfer function from the input vector
Let
Using (
Each coefficient
The
Impulse response of the matrix
Assuming that all signals have the same word length, the first inequality gives the worst-case variance error and therefore the fractional part word length will be selected taking into account this condition.
The variances of the sinusoidal input and output signals of the induction motor emulator are expressed in terms of the root mean square. Hence (
Assume that
Substituting (
Figure
SQNR as function of the signal fractional part word length.
The induction motor emulator is implemented using modular and standard design principles on a Xilinx Development kit, which contain a FPGA from SPARTAN III family, the XC3s200.
The emulator module requires important hardware resource. Therefore, the corresponding architecture is optimized in terms of consumed resources by the AAA methodology [
As in [
Proposed system architecture.
After the specification of the algorithm with data wordlength and sampling frequency, we propose to develop a modular architecture for the induction motor model to be implemented through an FPGA device.
Figure
Proposed system architecture.
The functional blocks of the global architecture are listed below. The UART (Universal Asynchronous Receiver Transmitter) module that provides a serial communication between the host PC and the implemented architecture. The UART allows both reconfigurations in real time of the induction motor model by tuning its coefficients and data acquisition to be visualized on the PC. To solve the dialogs between the UART implemented on the FPGA board and the PC, MATLAB's serial port interface is used. The input voltage stimuli module. It generates three digital values, which represent the three phases voltage. One can control the output waves amplitude and frequency in real time via the UART module. This module is used to test the induction motor (IM) module. The IM module that requires the most important hardware resources. It implements the induction motor model. The global sequencer module. It represents the control unit that generates a suitable timing schedule to control data path and other local sequencers.
The real-time simulation results presented in Figure
Simulated torque and torque produced by the implemented model on FPGA during a start-up.
The DTC is a well-known induction motor control strategy [ The UART (Universal Asynchronous Receiver Transmitter) module that provides a serial communication between the host PC and the implemented architecture. The stimuli module. It generates the references for the DTC control algorithm.
Real-time test bed.
The torque and the stator flux are collected from the serial interface and visualized under Matlab-Simulink environment. Figure
Real-time simulation results, obtained with DTC algorithm and the IM emulator: (a) steady-state stator flux vector locus, (b) estimated torque response to a step control from 0 N·m to 4 N·m.
This work has presented an optimized fixed-point format induction motor model intended for real-time simulation and emulation. With the analysis of the coupling between the sample rate and the data word length, this work has provided a theoretical guideline to find the optimal hardware implementation. The proposed architecture of the model has been successfully verified by the development and implementation of a real-time test bed that contains the AC-motor model and a DTC control algorithm.
The methodology for estimating the appropriate data word length may be applied to other various discrete-time system realizations.
This paper was supported by the Tunisian Ministry of High Education and Research: UR-LSE-ENIT-03/UR/ES05.