Conference Papers in Energy

Volume 2013 (2013), Article ID 168054, 10 pages

http://dx.doi.org/10.1155/2013/168054

Conference Paper

The Performance of a New Hybrid PLL in an Interconnected Renewable Energy Systems under Fault Ride Through Operation

Lenos Hadjidemetriou (Conference Presenter) and Elias Kyriakides

Department of Electrical and Computer Engineering, KIOS Research Center for Intelligent Systems and Networks, University of Cyprus, Nicosia, Cyprus

Received 3 January 2013; Accepted 14 March 2013

Academic Editors: Y. Al-Assaf, P. Demokritou, A. Poullikkas, and C. Sourkounis

Copyright © 2013 Lenos Hadjidemetriou and Elias Kyriakides. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

Modern renewable energy systems (RES) require fault ride through (FRT) operation in order to provide voltage and frequency support to the power grid when faults occur. The grid synchronization of a RES could be ensured by the appropriate operation of a phase-locked loop (PLL). A new hybrid PLL (dα βPLL) has recently been suggested by the authors and could operate accurately and faster than the other existing PLLs. The dα βPLL could be a very useful tool in the FRT operation of a RES, since the faster performance of the new PLL could boost the time performance of the FRT algorithm when a disturbance occurs. This paper investigates the performance of the flexible positive and negative sequence control (FPNSC) when the new dα βPLL is used. The paper also deals with the improvement on the FRT operation of the RES that could be obtained from the outstanding performance of the dα βPLL.

1. Introduction

The ever increasing penetration of renewable energy sources (RES) in the power grid requires the improvement of control techniques for the grid side converter (GSC) in order to ensure the synchronization and the appropriate operation of the RES during grid faults. Control methods in modern RES should be enhanced with fault ride through (FRT) capability in order to fulfill the grid codes for interconnected RES [1–3]. Especially in the case of small autonomous power grids, FRT operation of RES is particularly necessary in order to avoid cascading and catastrophic events.

The most important aspect for a RES when a fault occurs, is to first keep the synchronization with the power system and then to operate in a way to support the power grid. The grid synchronization is ensured in RES by estimating the phase angle and the amplitude of the grid voltage at the point of common coupling (PCC) through phase-locked loop (PLL) [4] as shown in Figure 1. Conventional PLL algorithms [5–7] are not able to operate successfully under unbalanced grid faults. A new hybrid PLL [8], named dPLL, has been suggested by the authors and could operate faster and with lower frequency overshoot than the ddsrfPLL [9] (which also operates accurately under unbalanced conditions) when a fault occurs.

Figure 1: An interconnected RES.

The enhanced PLLs (dPLL and ddsrfPLL) estimate the phase angle and the amplitude of the positive and negative sequence of the grid voltage. These quantities are provided to the FRT control algorithm in order to calculate the appropriate positive and negative reference currents, as described in [10–14]. FRT algorithms usually require accurate injection of positive and negative currents, and as a consequence, an advanced current controller needs to be used [15, 16]. The flexible positive and negative sequence control (FPNSC) [10–14] is implemented in this paper in order to evaluate the performance of the dPLL in an FRT operation. The FPNSC is an advanced FRT control algorithm that can provide voltage and frequency support to the power grid and can also easily adjust between injecting positive and negative sequence current, according to the required grid support.

This paper deals with the exploitation of the new dPLL in the operation of the FRT control techniques. Section 2 describes the structure and the advantages of the dPLL. The FPNSC FRT control method, that is, used in this paper is described in Section 3. The enhanced current controller for injecting both positive and negative currents is depicted in the same Section. A simulation model has been implemented for the purposes of this paper where the estimated phase angle and amplitude of the grid voltage from the dPLL are fed to the FPNSC algorithm in order to generate the reference currents for control of the GSC of an interconnected RES. In Section 4, simulation results for the FRT operation of the GSC are shown when the new dPLL is used. Some results are also shown in order to demonstrate the improvement to the performance of the FRT control that can be achieved by the use of the outstanding response of the dPLL.

2. The New Hybrid PLL

The new dPLL [8], as shown in Figure 2, is based on two decoupling cells and a control algorithm, that is, tracking the phase angle of the grid. The dPLL transforms the grid voltage in to two synchronous rotating frames: and . The frame rotates with positive synchronous speed and its angular position is . The frame rotates with the negative synchronous speed, and its angular position is  . The transformation is based on ,, and as shown in (1) and (2):

Figure 2: The structure of the proposed dfPLL.

The voltage vector , which consists of and under unbalanced conditions, could be transformed into the and axes according to (3):

Equations (3) are used as decoupling cells (see Figure 1) in order to decouple and by solving these equations to determine the use for the control dc-terms. Two decoupling cells are used in order to determine the positive and negative sequence grid voltage. The result of the decoupling cells are the and , which are almost dc-terms and through a low-pass filter (LPF), this could be used to monitor the grid voltage and also to feed the FRT control algorithm.

Therefore, the is transformed to the -stationary reference frame by using (1), and then a Proportional-Integral (PI) controller is used so that the estimated phase angle ) tracks the phase angle of the grid voltage ().

Through the decoupling of the positive and the negative sequence, a satisfactory operation is achieved during unbalanced faults, where the negative sequence voltage is not negligible any more. The new dPLL prevails the ddsrfPLL [9] (which also could operate appropriately under unbalanced conditions) since it is faster under the same frequency overshoot constraints as shown in Figure 3 [8]. The outstanding performance of dPLL could be very useful in order to obtain a faster time response of the FRT control when a disturbance occurs.

Figure 3: Simulation results for 1-phase to ground fault with 50% voltage sag in phase a. The dPLL operates faster than the ddsrfPLL under the same frequency constraint.

3. Fault Ride Through Control for an Interconnected RES

The power grid is a dynamical system, whose response is affected by many factors, including the occurrence of grid faults. Therefore, the interconnected RES should be designed considering that they should guarantee a proper operation under any grid voltage conditions. As a consequence, the control strategies in modern RES should be enhanced with FRT capability in order to fulfill the requirements of the grid operator regarding the voltage and frequency support during transient grid faults.

Grid faults are detected by the GSC as balanced or unbalanced low voltage at the PCC. Therefore, the positive and negative sequence of the grid voltage should be accurately estimated by an enhanced PLL, such as the new dPLL. The unbalanced grid voltage could affect the current injected by the converter and could cause the emergence of nonsymmetrical or nonsinusoidal currents. These currents, in combination with unbalanced grid voltage, could cause oscillations in the active and reactive injected power. Hence, the design of an FRT algorithm requires an analytic study of the power theory under unbalanced conditions, as described later in Section 3.1.

The proper operation of the FRT control may require the injection of unbalanced currents. Conventional three-phase current controllers are not suitable for injecting unbalanced currents. As a consequence, improved current controllers are required in order to satisfy the proper injection of the positive and negative sequence reference currents of the FRT algorithm as shown later in Section 3.2.

The FPNSC algorithm is presented later in Section 3.3, where the knowledge of the grid voltage (, ) which is required for the FRT algorithm is provided by the new dPLL. The FPNSC algorithm is an advanced FRT control which could adjust, in a very flexible way, between positive and negative currents injection according to the purpose of the FRT control.

3.1. Power Theory under Unbalanced Grid Conditions

According to the instantaneous power theory [10, 17], the instantaneous active and reactive power supplied by the GSC of an interconnected RES can be calculated as:

where

is the voltage vector at the point of common coupling (PCC), is the injected current vector, and is an orthogonal version (90° leaded) of the original voltage vector . The equations presented here are valid for any reference frame, but for the purposes of this paper, a synchronous reference frame dq is mainly used.

During unbalanced grid conditions, the voltage and the current could be written as a summation of the positive and the negative sequence components:

Therefore, the equations for the active and reactive power in (4) could be rewritten as:

From (7), it is obvious that the existence of negative sequence voltage or current (unbalanced disturbances) could give a rise to oscillations in active and reactive power.

3.2. Control Structure for Unbalanced Current Injection

The appropriate operation of the FRT control requires the injection of positive and negative sequence currents by the current controller. Conventional current controllers are inappropriate for operating under these conditions due to the cross-coupling between the currents on positive () and negative () synchronous reference frames [10, 15].

The existence of the negative sequence current () gives rise to a oscillation on overlapping the dc signal on -axis and vice versa, as shown in (8)

A suitable current controller should attenuate the oscillation of the and in order to achieve full control of the injected currents under unbalanced conditions. A double synchronous reference frame current controller enhanced with some filter [10, 15, 16] could successfully decouple the positive and negative measured currents as illustrated in Figure 4. The measurement currents transform to both positive and negative synchronous reference frames (SRF). Then, the negative dc-term is isolated by a low-pass filter (LPF) from the negative SRF and transformed through the in order to attenuate the oscillation of the current on positive SRF and vice versa. This cross-feedback decoupling network achieves the complete cancelation of the oscillations in the measured currents with a fast dynamic response. Therefore, the dc-signals and are fed to the current controller in order to obtain full control of the positive and negative injected currents.

Figure 4: Decoupled double synchronous reference frame current controller using a decoupling network based on the measured currents.

3.3. FPNSC Algorithm

The FPNSC algorithm [10–14] is an FRT control which could provide voltage and frequency support to the grid under fault condition. The FPNSC algorithm generates the reference currents that will feed the current controller during the fault, so the interconnected RES provides the appropriate support to the grid. The reference currents depend on the active and reactive power reference and the strategy of the FRT control. The advantage of FPNSC is the easy adjustment according to the control plan, so the control could aim to rise the faulty positive voltage or to minimize the unbalanced voltage condition, or both.

The reference currents could be determined independently, since

where and can be considered as the active and reactive reference current vector, respectively.

The active reference current can be written as a function of a positive and a negative sequence conductance ( and ) and reactive reference current as a function of a positive and a negative sequence susceptance ( and ) as described by

where ,,, and can be determined by

where and are certain set-points for the injection of active and reactive power.

The current references are composed by both sequence components simultaneously so it is necessary to introduce the scalar parameters and in order to regulate the contribution of each sequence on the reference currents as shown in (12). The parameter regulates the active, and the parameter regulates the reactive reference current:

Finally, the current reference is given as the summation of (12) and is determined by the following equation:

The value of and can easily be adjusted and regulate the injection current between positive and negative sequence. For example, if there is a balanced voltage drop at the PCC, will be set at 1 in order to inject just positive sequence reactive current in order to increase the voltage of the symmetrical voltage sag. On the other hand, if unbalanced voltage sag is observed at the PCC and is set to zero, then the RES will inject just negative sequence reactive currents, and as a consequence, the negative sequence voltage will be reduced and the grid voltage will become more symmetrical.

The proper operation of the FPNSC algorithm requires the estimation of the maximum active and reactive power set-points in order to avoid exceeding the current rating of the GSC. A further analysis for the estimation of the maximum power is presented in [10] and concludes with the following equation:

where is the peak current for each phase and each is correlated with a value of the angle , as shown in Table 1, where the and are the positive and negative sequence phases of the grid voltage. The peak current should never exceed the power converter rated current .

Table 1: Peak current values for each phase.

Phase
Angle

In order to calculate the maximum reactive power for the converter during the fault, it is necessary first to set the active power set-point and then to find the three possible solutions for (14), one for each phase. The maximum reactive power set-point is given by the minimum of the three solutions .

In case that the , then the solution of (14) leads to

Therefore, the maximum reactive set-point is given by the minimum of the three possible values calculated by (15).

4. Simulation Results

4.1. Simulation Model

A dynamic simulation model has been implemented in MATLAB/Simulink in order to evaluate the performance of the dPLL in an interconnected RES under FRT operation. The control structure for the GSC with FRT capability is illustrated in Figure 5. The dPLL observes the grid voltage at the PCC and estimates the ,,, and, which are necessary for the FRT algorithm. The FPNSC generates the positive and negative sequence reference currents which are fed to the current controller. An enhanced current controller, as the one shown in Figure 4, is used in order to achieve the appropriate current control in both positive and negative injected currents.

Figure 5: Control structure for the GSC with FRT capability using dPLL for the synchronization.

In order to obtain a more realistic scenario, the RES is connected to a small power grid. The 10 MVA GSC of a RES is interconnected with a small autonomous power system, as shown in Figure 6. In this test bed system, some faults will be applied in order to observe the performance of the dPLL and the response of the FRT control under fault conditions.

Figure 6: A 10 MVA RES interconnected with a small power system.

A number of case studies are presented in the next subsections in order to demonstrate the performance of the FRT control. Figure 7 shows the time schedule of the FRT control that will be used in these study cases. The simulation starts with the system under normal operation, and at 0.5 s, a fault occurs. The GSC continues to operate based on the conventional control algorithm until 0.6 s, where the FRT control is applied. The RES operates with FRT capability until 0.9 s when the fault is cleared.

Figure 7: Time schedule for the FRT control during the fault.

4.2. FRT Control: Injecting Full Positive Reactive Power

This case study shows the simulation results for the FRT control when a 1-phase to ground fault occurs in the middle of line 2, as depicted in Figure 5. The performance of the FRT control when the FPNSC algorithm is set to inject full positive reactive currents is demonstrated in this simulation experiment. Therefore, the set-point for the FPNSC algorithm is set to zero, and the is calculated through (15). The full positive reactive power is achieved by setting in (13) in the FPNSC algorithm. The simulation results are shown in Figure 8. The effect of the FPNSC FRT algorithm, which is applied at 0.6 s, is clearly the rise of the positive sequence voltage at the PCC from 0.489 kV to 0.542 kV. The negative sequence voltage is insensitive during the application of this algorithm. Also, the limitation in reactive power set-point through (15) in the FPNSC algorithm allows the proper operation of the GSC without any violation in the current ratings of the GSC (12 kA). The injection of full positive sequence reactive power allows the increase of the voltage during the fault, but it cannot improve the asymmetrical form of the grid voltage during the fault.

(a)

(b)

(c)

(d)

Figure 8: Simulation results for the performance of the FPNSC algorithm for full positive sequence reactive current injection during FRT operation.

4.3. FRT Control: Injecting Full Negative Reactive Power

The performance of the FRT control when the FPNSC algorithm is set to inject full negative reactive currents is demonstrated in this simulation under the same fault condition as mentioned in the previous case study in Section 4.2. Again the set-point for the FPNSC algorithm is set to zero, and the is calculated through (15). For injecting full negative reactive currents, the parameter is set to zero in (13). The simulation results for injecting full negative reactive power are shown in Figure 9. The effect of the FPNSC FRT algorithm, which is applied at 0.6 s, is clearly the decrease of the negative sequence voltage at the PCC from 0.076 kV to 0.017 kV. The positive sequence voltage is insensitive during the application of this algorithm. Also, the limitation in the reactive power set-point through (15) in the FPNSC algorithm allows proper operation of the GSC without any violation in the current ratings of the GSC. The injection of full negative sequence reactive power allows the smoothing of the unbalance of the grid voltage during the fault, but it cannot contribute so much in the increase of the voltage level as it is illustrated in Figure 9.

(a)

(b)

(c)

(d)

Figure 9: Simulation results for the performance of the FPNSC algorithm for full negative sequence reactive current injection during FRT operation.

4.4. Contribution of the New PLL in the Time Response of the FRT Algorithm

The purpose of this case study is to show the contribution of the new dPLL in the performance of the FRT algorithm. The new dPLL could successfully be used in FRT algorithms, as has been shown in the previous subsections. In this case study, both ddsrfPLL and dPLL has been set in order to have the same frequency overshoot ( Hz) under a 2-phase to ground fault at the middle of line 2, as shown in Figure 6. The frequency overshoot of the PLLs is critical when a fault occurs because any violation of the frequency limits could cause the disconnection of the RES from the grid according to the grid regulations. As mentioned in [8], the dPLL is expected to operate faster than the ddsrfPLL under the same frequency overshoot. This means that the dPLL could estimate faster the phase angle () and the positive and negative sequence ( and ) of the grid voltage when the fault occurs. The above mentioned ,, and are used in FPNSC algorithm in order to calculate the reference currents. Therefore, a faster estimation of these quantities through dPLL could cause a faster response of the FRT algorithm.

For this case study at 0.6 s, the FPNSC algorithm is applied in two similar systems. The first system (FPNSC-dPLL) is using the dα βPLL to estimate the ,  , and , and the second system (FPNSC-ddsrfPLL) is using the ddsrfPLL to estimate these quantities. The faster estimation of the and from dPLL allows the FPNSC-dPLL system to set the reference currents ( and ) faster than the FPNSC-ddsrfPLL system as shown in Figure 10. This leads to the fact that the injected currents are adjusted in a faster way as shown in Figure 11, and as a consequence, the FRT algorithm is applied faster in the FPNSC-dPLL system. As shown in Figure 11, the meas tracks the ref within 47.3 ms using the FPNSC-dPLL system instead of 58.7 ms of settling time using the FPNSC-ddsrfPLL system. This translates to a 19.4% faster time response of the FRT algorithm when the new dPLL is used to observe the phase and the amplitude of the grid voltage.

(a)

(b)

Figure 10: Positive sequence reference currents generated by the FPNSC algorithm. The blue current depicts the reference produced by the FPNSC-dPLL system, and the green is the reference produced by the FPNSC-ddsrfPLL system.

Figure 11: The settling time required from meas to track the refis lower using the FPNSC-dPLL system than using FPNSC-ddsrfPLL system.

5. Conclusions

The use of the new dPLL in the FRT algorithm is demonstrated in this paper. The dPLL could successfully be used in the FRT algorithms in interconnected RES in order to provide support to the grid during faults. The outstanding response of dPLL could lead to a faster performance of the FRT algorithm. The faster performance of the FRT control algorithm in RES is very critical when a fault occurs in the power system in order to avoid catastrophic blackouts.

Acknowledgments

This work was cofunded by the European Regional Development Fund and the Republic of Cyprus through the Research Promotion Foundation (Project NEA YΠOΔOMH//0308/26).

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