Reduced Precision Redundancy for Satellite Telecommand Receiver Module on FPGA

: A novel and highly efficient design of a Software defined radiation tolerant baseband module for a LEO satellite telecommand receiver using FPGA is presented. FPGAs in space are subject to Single Event Upsets (SEUs) due to high radiation environment. Traditionally, Triple Modular Redundancy (TMR) is used for mitigating Single Event Upsets (SEUs). The drawback of using TMR is that it consumes a lot of hardware resources and requires more power. Reduced Precision Redundancy (RPR) can be a viable alternative of TMR in digital systems for arithmetic operations. This paper uses the combination of RPR and TMR for mitigating SEUs. The designed module consumes less resources on FPGA and has Bit Error Rate (BER) identical to theoretical, apart from degradation due to implementation losses. An improved Costas loop and timing recovery algorithm are implemented for achieving carrier recovery and bit synchronization. The hybrid approach mitigates SEUs while consuming 26% less resources than a customary TMR protected receiver.


INTRODUCTION
this purpose.The drawback of using TMR is that it Reconfigurability and adaptability are one of the power [3].Thus; there has been a constant effort to find most desirable features of modern space technology.
an alternative to the TMR technique.Shim, et al. [4] FPGA provides this flexibility along with good introduced Reduced Precision Redundancy (RPR) as part performance.They have become an integral part of of a power-reduction technique for ASIC-based systems, satellite systems for over a decade.Their high Snodgrass [5] demonstrated variation of RPR on FPGA to computational capacity combined with small size and limit high magnitude errors of arithmetic operations in light weight makes them a preferable choice over other high radiation environment.Pratt, B., et al [6] has digital systems.The ability to reconfigure FPGA with an presented the hybrid approach using RPR and TMR for updated functionality reduces the hardware requirement FPGA based communication systems. in space craft [1].
This paper presents a highly efficient design of a However, FPGA's face some severe problems in the software defined radiation tolerant module for a LEO space environment.The high energy particles in space satellite telecommand receiver.The proposed module uses may interact with memory cells within an integrated circuit the combination of RPR and TMR for SEU mitigation.To and can change their logic state [2].This alteration may the best of author's knowledge, this hybrid approach is disrupt the operation of a digital system defined by not being implemented to a satellite telecommand receiver memory cells.FPGAs contain large array of memory cells module using Binary Phase Shift Keying (BPSK) which makes them more susceptible to single event modulation.During literature review, it was found that the upsets (SEUs).
BPSK receiver of Maya, J.A., et al [7] and our design has In order to operate properly in space, some mitigation same technical specifications.So it was taken as a bench techniques need to be applied in FPGAs.Traditionally, mark for fair resource utilization.The designed module Triple Modular Redundancy (TMR) has been used for consumes less resources and its Bit Error Rate (BER) is consumes a lot of hardware resources and requires more approaching to 10 .This paper evaluates the effect of output among them.TMR, however, consumes a lot of 6 SEUs on the BER performance of a telecommand resources and power.On the other hand a resource receiver.
efficient alternative to TMR for arithmetic operations is The paper is organized as follows.Section II explains "RPR".In this paper we have presented the application of the impact of high radiation environment of space on RPR to the arithmetic operations involved in the design of FPGA and introduces the concept of RPR.In section III, a telecommand receiver.the detailed implementation of our proposed telecommand receiver and SEU mitigation technique using RPR is Reduced Precision Redundancy: In RPR, the full precision described.Section IV shows the hardware co-simulation (FP) module to be protected is replicated twice with results.Section V presents the conclusions drawn from reduced precision (RP) as shown in Fig. 1.The decision the results.
block uses the output of RP modules to determine the

FPGA in Space Environment
Single Event Upsets: In SRAM based FPGAs, a large area if ((|FP -RP1 | > T ) AND (RP1 = RP2 )) is composed of memory cells.These memory cells contain output = RP2 else output = FP both user data and circuit configuration data that defines the functionality of a system.When high energy charged Threshold (T ) value is a very critical parameter in particles such as neutrons and alpha particles present in RPR.If T is very small, false error detection will occur and the space environment interact with SRAM cells, they if T value is high, error will not be detected.In order to occasionally invert there logic state.This phenomenon avoid this problem, the T value is set equal to the is called as SEU [2].The inverted logic state can be difference between the FP and RP modules' outputs as both of user data or configuration data and can cause shown in (1) when there is no error.unpredictability in systems behavior.The SEU directly affects the bit error rate performance of a communication T = | FP -RP | (1) receiver.Four general classes of SEUs are identified according to their effect on BER [6].
The reduced precision redundancy factor (k) is a In class 1 SEUs, lower order bits of arithmetic Therefore, the size of RP modules and decision block must operations (such as output of accumulator or be chosen in such a way that they consume less resource coefficient of a filter) are affected.They are 30%-77% than TMR while mitigating SEUs.RPR can be applied to of the total SEUs.arithmetic operations of any size and complexity.In class 2 SEUs, middle order bits of arithmetic Whether, it is a simple FIR filter or a complex receiver.operations are affected.They are 17%-64% of the Unlike TMR, RPR is not suited for every application.total SEUs.3) In class 3 SEUs, higher order bits of It is only applicable to those arithmetic operations that arithmetic operations are affected.They cause severe can be approximated with a reduced precision.degradation in circuit performance and are unacceptable.They constitute 3%-4% of the total Implementation of Telecommand Receiver and Seu SEUs.

Mitigation In class 4 SEU, clock distribution, global reset
Telecommand Receiver: This paper focuses on the signals MSB of filter or threshold comparator are implementation of a baseband processing module on affected.They are termed as "catastrophic" and FPGA and its SEU mitigation.The data rate of the reduced BER to ½.They constitute 2%-4% of the designed system is set to be 1Mbps and baseband carrier total SEUs.frequency is 4 MHz.BPSK modulation is used in So class 3 and 4 SEUs are more critical and need to spectral performance, fast transfer rates and good BER [8].be mitigated proficiently.Various techniques have been The algorithms and concepts used in the receiver used in the past to mitigate class 3 and 4 SEUs, the most system are validated using high level design tools popular being the TMR technique [6].In TMR, three tradeoff between mitigation cost and SEU performance [6].
telecommand link due to its strong anti-interference, good binary shift registers without using embedded multipliers.
Coherent demodulation approach is adopted due to its good BER and high SNR performance as compared to non-coherent [8].The designed system as shown in Fig. 2 contains following sub modules: Carrier recovery, integration, bit synchronization and decision block.
The Costas loop is used for achieving the carrier recovery of BPSK modulated signal as shown in Fig. 3. Carrier recovery is performed for extracting the RF carrier from a received modulated signal which is then used to sampling frequency to half for the rest of the system.This down converted signal is mixed by the 14 x 14 bits multiplier of In-phase channel (I-channel) and Quadrature channel (Q-channel) with sine and cosine signals respectively.These orthogonal sinusoids are generated through Numerical Controlled Oscillator (NCO).The NCO is implemented by using Direct Digital Synthesizer The demodulated signal is applied to the integrator module.It accumulates the signal over one bit duration before resetting itself which produces triangular wave at the output.The resetting of integrator is the core of timing synchronization and is performed exactly after one bit duration.The design of integrator module is accomplished by using an accumulator bock with the timing control module.Integrator's output is processed by the bit Fig. 5: Early Late Gate Sampling block synchronization unit which uses an improved form of early late gate sampling algorithm as shown in Fig. 5.The algorithm is implemented by using relational operators rather than arithmetic operators in order to avoid any floating point arithmetic.It uses three samples (i.e.early (E), present (P) and late (L)) and a threshold value (T ) to detect the peak of the signal which h determines the sampling instant for the bit.The algorithm used is as follows: The peak detect signal is sent to the data sampler and and mixers of I and Q channel consists bulk of arithmetic preamble match modules.Data sampler consists of a operations.In fact they constitute more than half of the counter along with relational operators to sample the total design resources.This makes them ideal contenders signal.The preamble match module is composed of a for RPR.Phase detector comprises of multiplication Block RAM to store the preamble bits and relational operation, which is better suited for RPR then TMR [12].operators for comparing the preamble with sampled bits.
Loop filter is composed of binary shift registers which When the peak detect signal is asserted, the preamble makes RPR ineffective.The decision block contains no module compares the sampled bits from data sampler with arithmetic operation so it cannot be protected using RPR. the pre-stored preamble bits.After successful matching of Experimentally, it was determined that due to the high cost the preamble, the decision block starts sampling the of RPR decision blocks, it is more efficient to apply TMR integrator module output and thus data bits are recovered to NCO, integrator and to the bit synchronization module.at the output port.The complete receiver implementation The diagram of a telecommand receiver module is shown is pipelined to maximize the timing performance.It has in Fig. 6 with annotations indicating the type of mitigation been observed during simulations that the data sampling technique applied to each system block.at integrator's output produces good BER than sampling The suitable value of RPR factor (k=7) is determined of demodulated output from Costas loop.
which reduces the size of RPR module while ensuring SEU Mitigation: As mentioned earlier, RPR is not suited be the maximum difference between FP and RP to all types of applications and designs.For applications modules.comprises of arithmetic and non-arithmetic operations, combination of both RPR and TMR is the best approach RESULTS for mitigating SEUs [6].The baseband processing module of a telecommand receiver is composed of arithmetic and The proposed design of the telecommand receiver non-arithmetic operations.
module is implemented on Xilinx System generator.The The designed system was analysed to identify the module was hardware co-simulated using Spartan 3E potential areas where RPR application would cause XCS3E500E-4FG320 FPGA as shown in Fig. 7. Hardware significant reduction in resource consumption for the Co-simulation incorporates FPGA hardware into the and its comparison with Maya, J.A., et al [7] is presented HWCOSIM_Received_Bits e) HW COSIM _ in Table 1.It can be seen that the designed system SynLock consumes 50% less multipliers, 1% less slices and 5% less  Sync_lock signal (d) and data received bits (e) results from hardware co-simulation.BER analysis of the receiver module is performed using "bertool" provided in MATLAB.The BER performance of the overall designed system is calculated using Monte Carlo simulation.Fig. 9 presents a comparison between the BER of the proposed system and the ideal BPSK receiver in AWGN channel.It can be seen that the proposed systems BER is almost identical to the BER of the ideal receiver.The slight degradation in BER graph of the designed module is due to the implementation losses.
4-input LUTS as compared to [7].The timing recovery unit of the proposed system consumes almost 60% less slices as compared to [7] and uses no multiplier.The SEU effect is emulated by inverting a bit in the design.For this purpose, loop filter is selected because it plays a critical role of keeping the demodulator and receiver in the desired working area and an upset in it would have a major impact on receiver's performance.Class 1 SEU, is introduced by inverting the LSB of the loop filter.Class 2 SEU is simulated by flipping the middle order bit of the loop filter.Higher order bit is flipped for class 3 SEU.The MSB of the loop filter is inverted for class 4 SEU.The effect of SEU on BER performance with It can be observed from Fig. 10, that all classes of  -------------------------- This work [7] This work [7] Total Avail.TMR and RPR application increases the overall size of the designed system by introducing its replica's.Therefore, a different FPGA platform was required that can meet the resource requirements.We decided to implement TMR and the combination of RPR and TMR using Virtex 4 XC4VSX55-10FF1148 FPGA.Both methods mitigate SEUs successfully and their resource comparison is presented in Table 2.The results show that the hybrid approach is more efficient in terms of resources as compared to TMR.The combination of RPR and TMR consumes 26% less slices, 42% less slice flip-flops and almost 18% less 4-input LUTS as compared to TMR.

CONCLUSION
This paper presents a new technique for software defined radiation tolerance of baseband module for a LEO satellite telecommand receiver.The combination of RPR and TMR is used in the receiver module for SEU mitigation.This hybrid approach has shown to be very effective and consumes far less resource than a customary TMR protected receiver.The adopted scheme uses a resource efficient implementation of Costas loop for carrier recovery and early late gate sampling algorithm for timing recovery.The optimized receiver module has BER performance identical to theoretical, with minor degradation due to implementation losses.It has been concluded that by focusing on targeted implementation of RPR in systems involving arithmetic operations, a lot of resources can be saved as compared to complete TMR system.Future work would include RF Front end connected with the FPGA hardware to perform real time measurements and changing the RPR redundancy factor (k) to evaluate its impact on systems BER performance.
(i.e.MATLAB/SIMULINK) providing the flexibility to replicas of the same circuit are made and they are simulate, debug and analyze the functionality of each connected to a voter block which selects the correct working block.Moreover, they accelerate the design error in FP module as follows:

Fig. 1 :Fig. 4 :
Fig. 1: Block diagram of an n-bit FIR filter protected with recover the data from it [9].The incoming baseband signal k-bit RP modules is first down sampled by a factor of two which reduces the compiler 4.0 (DDS 4.0) in FPGA with 96 dBc Spurious Free 18-bits with the output signal width set to 14 bits.These values ensure least resource utilization along with desired performance.The I and Q channel multiplier outputs are passed through a fifth order low pass FIR filter to remove high frequency components.Our designed filters are realized using Direct Form symmetric architecture as shown in Fig.4.This architecture uses the symmetry in the coefficients of filter and requires half the multiplier and adders compared to other architectures thus, consumes less resources on FPGA.Moreover, one shift operation which further reduces resource consumption.The low pass filters in each channel are designed wide enough to pass the data modulation without distortion [10].The filtered I and Q channel signals are pass on to Phase Detector (PD) block.It extracts the phase difference between I and Q signals.It is implemented by using small angle approximation [11].Loop filter removes the high frequency leakages of the phase detector.It provides a smooth and stable 18-bit control word to the NCO for modifying its output frequency and phase with respect to input signal.When the NCO's generated carrier frequency and phase are synchronized with the incoming signals at the I channel.The designing of loop filter is a very The designed Costas loop can demodulate input signal with Doppler shifts up to 10 percent of the carrier frequency.

Fig. 9 :
Fig. 9: BER of Telecommand Receiver respect to different classes is shown in Fig.10.

Table 1 :
Resource Comparison of Proposed Receiver Module and [7] on Spartan 3E

Table 2 :
Resource Comparison of Tmr and Rpr+tmr on Virtex 4