An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm2) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).
Conventional multistandard wireless mobile terminals contain multiple RFICs. To reduce production costs, one-chip wideband RF LSI systems are desired. A great effort is being made to develop wideband and/or multiband RF solutions using highly scaled advanced CMOS processes. The use of such processes is beneficial to
In designing VCOs which generate signals in RF systems, ring-type VCOs (ring VCOs) are more attractive than LC-resonant-type VCOs (LC VCOs) in terms of their small area and wide frequency tuning range since they do not use large passive devices. However, they have poor phase noise with relatively high power consumption. Nevertheless, low-phase-noise ring VCO is still a possibility if some noise-suppression mechanism is applied. One of available options would be injection locking.
In the early days, Adler [
This paper describes a study on a ring-VCO-based PLL with pulse injection locking as a potential solution to realize a scalable inductorless PLL, which can generate wideband frequency signal with low supply voltage. Usually, the frequency range utilized consumer RF applications, such as wireless LAN a/b/g/n, Bluetooth, and digital TV (DTV), is very wide and spreading from 400 MHz to 6 GHz. Table
Target performance.
VCO | Ring |
Frequency range | 6–12 GHz |
Phase noise at 1 MHz offset | −100 dBc/Hz |
CMOS process | 90 nm |
Supply voltage | 1.0 V |
In addition, the proposed PLL is augmented with high-frequency half-integral subharmonic locking in order to improve its phase-noise performance. In Section
Figure
Injection-locked PLL with pulse injection.
PLLs that use ring type VCOs are required to have a wide loop bandwidth of the phase-locked loop for lowering their poor phase noise characteristics. However, there is a trade-off between the loop bandwidth and the stability of PLLs. In general, the loop bandwidth (
Phase-noise reduction with a charge-pump PLL and injection locking.
The overall ILO output phase noise is obtained by adding the noise contributions in an ILO. Assuming that
In the proposed PLL, there are two kinds of phase locking mechanism: one is a phase-locked loop, and the other is pulse injection locking. In general, either of them is enough for phase locking. However, those two mechanisms are combined to get a wide frequency range operation with a low-phase-noise performance. The phase-locked loop, which uses a charge pump for controlling the oscillation frequency, is implemented to ensure correct frequency locking over the entire VCO tuning range. The final phase locking is done by injection locking to reference signal [
A paper on half-integral subharmonic injection locking based on the use of a ring VCO has been presented [
Voltage and current waveforms at differential output nodes of a VCO; (a) integral subharmonic locking (
One advantage of using half-integral subharmonic locking is to be able to use high-frequency reference signal and can make the locking range of injection locking,
As shown in (
One solution is to employ cascaded oscillators [
Concept of the cascaded ILOs.
The output signal of VCO1 is injected into VCO2 and locked to the output of VCO2 with the same process occurred in VCO1. Also, the output phase noise of VCO2 with injection locking can be expressed as follows:
Figure
Dividers ratio in Figure
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32 | 24, 36 | 1, 8 | 4, 8 |
Proposed cascaded injection-locked PLL (CPLL) with pulse injection.
Figure
(a) Proposed differential delay cell, (b) two-stage differential VCO of MPLL with a bias-level-shift circuit.
The proposed ring VCO is shown in Figure
A tristate phase/frequency detector (PFD) is implemented, which consists of two D-flip flops, delay-path inverters, and an AND logic. The PFD detects phase and frequency difference between the reference signal and the divided VCO output and generates output pulses of
Figure
Sooch cascode current mirror circuit.
Proposed current switching charge pump (CP) that employs Sooch cascode current mirror is shown in Figure
Proposed charge-pump (CP) circuit and loop filter (LF).
Figure
Charge-pump output current versus the control voltage (
A second-order lag-lead filter that consists of a register and two capacitors is implemented as a loop filter (LF) of the loop to suppress the charge-pump ripple. (
The frequency divider consists of differential pseudo-nMOS latches to minimize chip area and achieve low power consumption [
The loop dynamic characteristics are designed to have the unity-gain bandwidth of 2.8 MHz and phase margin of 16° (VCO gain: 5 GHz/V,
To achieve subharmonic locking, an AND-based pulser is used, which is able to tune the pulse width below 40 ps by the analog control. Also, a variable time-delay unit (
The proposed ring VCO used in RPLL is based on a four-stage pseudo differential ring oscillator. The same delay cell shown in MPLL (Figure
The tristate PFD and CP presented in Figure
As a loop filter (LF), a second-order lag-lead filter is implemented. The filter consists of a register (
Figures
Chip micrographs; (a) proposed VCO and (b) proposed PLL.
During free-running operation, the frequency tuning range of the VCO was from 6.35 GHz to 11.5 GHz as shown in Figure
Measured frequency tuning range of the VCO.
Phase noise characteristics of the VCO and PLL at
Measured phase noise characteristics at 7.2 GHz from the VCO and PLL output without and with injection locking.
Figure
Calculated phase noise by using (
Measured phase noise characteristics at 10.8 GHz from the VCO and PLL output without injection locking.
Phase noise characteristics of the VCO and PLL at
Figure
A chip micrograph of the proposed cascaded PLL.
Figure
Measured phase noise characteristics of RPLL output at 1.6 GHz.
Figure
Measured phase noise characteristics of CPLL output at 7.2 GHz.
Usually, spurs are induced by periodic phase shift due to injection locking. The spur level can be expressed as follows:
Calculated phase noise characteristics by using (
Calculated phase noise by using (
Figure
Measured phase noise characteristics of CPLL output at 9.6 GHz.
The PLL generated reference spurs of lower than
Measured frequency spectra of CPLL output (a) at 7.2 GHz and (b) at 9.6 GHz.
A performance summary at the output frequency of 7.2 GHz of the fabricated chips are given in Table
Performance summary at
This work | MPLL VCO | MPLL | CPLL | |
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7.2 | |||
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— | 300 | 50 | |
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300 | 300 | 200 | 1600 |
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24 | 24 | 36 | 4.5 |
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Power consumption [mW] | 8.4 | 14 | 25 | |
Area [mm2] | 0.0014 | 0.080 | 0.11 |
A performance comparison of the PLL with other PLLs that were designed using various kinds of phase-locking methods is given in Table
Performance comparison of PLLs.
Reference | CMOS Technology |
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Power [mW] | Area [mm2] | VCO |
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This work |
90 nm |
1.6 | 32 |
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11 (sim.) | 0.031 | Ring |
7.2 | 144 |
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25 | 0.11 |
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9.6 | 192 |
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27 | ||||
[ |
90 nm | 20 | 20 |
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38 | 0.46 | LC |
[ |
90 nm | 9.24 | 35 |
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56 | 0.09 | Ring |
[ |
0.18 |
8.98 | 17 |
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58 | 0.77 | LC |
[ |
0.18 |
8.45 | 32 |
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117 | 5.5 | LC |
*Normalized in-band phase noise =
An inductorless PLL architecture, using the combination of a phase-locked loop, and injection locking with a ring VCO was proposed. The proposed CPLL that consists of two PLLs was designed in order to generate high-frequency output signals with low-frequency external reference signals. High-frequency half-integral subharmonic injection locking to improve the phase noise characteristics of the inductorless PLL was implemented.
The injection-locked PLL was fabricated by adopting 90 nm Si CMOS technology. A 1 MHz-offset phase noise of
This work was partly supported by STARC, KAKENHI, MIC.SCOPE, and VDEC in collaboration with Agilent Technologies Japan, Ltd., Cadence Design Systems, Inc., and Mentor Graphics, Inc. The authors also acknowledge the JSPS Research Fellowship for Young Scientists from the Japan Society for the Promotion of Sciences.