Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost.
Reversible logic has attractive perspective of constructing digital devices that can realize computing unit with almost zero power dissipation. Landauer [
Though, reversibility recovers bit loss, but it is not able to detect bit error in circuit. Fault-tolerant reversible circuits are capable of preventing errors at outputs. If the system itself made of fault-tolerant components, then the detection and correction of faults become easier and simple. In communication and many other systems, fault tolerance is achieved by parity. Therefore, parity-preserving reversible circuits will be the future design trends to the development of fault-tolerant reversible systems in nanotechnology.
On the other hand, QCA (Quantum-dot Cellular Auto-mata) is considered to be promising in the field of nanotechnology due to their extremely small sizes and ultralow-power consumption [
Significant contributions have been made in the literature towards the design of arithmetic units in [
This motivates us to design a fault-tolerant reversible ALU architecture considering QCA technology. A cost-effective realization of a fault-tolerant reversible adder (FTRA) is first introduced. It is then utilized to synthesize the desired fault-tolerant reversible arithmetic logic unit which outperforms the efficiency of existing designs in terms of design complexity and quantum cost. The major contributions of this work around reversible QCA architecture can be summarized as follows: realization of generic fault-tolerant reversible adder having parity-preserving logic with cost effective quantum cost; the presented fault-tolerant reversible adder block is used to realize different arithmetic circuit such as full adder, subtractor, ripple carry adder, and carry-skip logic; synthesis of a fault-tolerant reversible arithmetic logic unit (ALU) using proposed adder; application of the proposed adder in QCA nanotechnology with effective fault tolerance of 47.38% in the presence of all possible single missing/additional cell defects.
Simulations using QCADesigner [
Elementary quantum logic gates: (a) NOT, (b) exclusive OR, (c) square root of NOT (SRN), and (d) Hermitian matrix of SRN.
QCA basics.
Structure of a QCA Cell
QCA cell with two different polarizations
Majority voter
Inverter
Wire crossing
Few fault-tolerant reversible 3 × 3 gate-like Feynman double gate (F2G), Fredkin (FRG), NFT, and so forth and 4 × 4 gate like MIG are already investigated.
In [
In communication and many other systems, fault tolerance is achieved by parity. A parity-preserving reversible gate, when used with an arbitrary synthesis strategy for reversible logic circuits, allows any fault that affects no more than a single logic signal to be detectable at the circuit's primary outputs [
Truth table of proposed fault-tolerant adder.
A | B | C | D | E | P | Q | R | S | T |
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0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 |
0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 |
0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |
0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |
1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 |
1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 |
1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |
1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 |
1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
Proposed fault-tolerant reversible adder.
Block diagram fault-tolerant adder
Quantum implementation of fault-tolerant adder
A fault-tolerant reversible full adder and subtractor circuit using the newly proposed FTRA gate is shown in Figure
Performance analysis of different fault-tolerant full adders.
Parameter | [ |
[ |
[ |
[ |
Proposed |
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Gate count | 5 | 6 | 2 | 4 | 1 |
Quantum cost | 25 | 18 | 14 | 11 | 8 |
Garbage outputs | 4 | 6 | 3 | 3 | 3 |
Constant inputs | 2 | 5 | 2 | 2 | 2 |
Logical calculations |
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Implementation of different logic circuit with proposed FTRA.
Fault-tolerant full adder and subtractor
Fault-tolerant ripple carry adder
Fault-tolerant carry-skip adder
The advantage of our method is in the implementation of this logic at gate level. Thus, once the required gates have been designed and an appropriate synthesis framework has been established, fault-tolerant implementation requires no extra expenditure in design or verification effort.
The reversible fault-tolerant 1-bit ALU is designed with one FTRA gate, two Fredkin gates, and four Double-Feynman gates. Thus the design uses a total of 7 gates and has a quantum cost of 26 (Figure
Different function of ALU.
C0 | C1 | C2 | Output | Function |
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0 | 0 | 0 | AB | AND |
0 | 0 | 1 |
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NOR |
0 | 1 | 0 |
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NAND |
0 | 1 | 1 |
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OR |
1 | X | 0 |
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ADD |
1 | X | 1 |
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SUB |
Fault-tolerant ALU with proposed FTRA.
Implementation of n-bit fault-tolerant ALU.
To demonstrate the application of the proposed fault-tolerant design approach to reversible adder in emerging nano-technologies, Quantum-dot cellular automata (QCA) technology is considered because reversible logic has potential applications in QCA computing. The QCA implementation of the proposed FTRA gate is shown in Figure
QCA implementation of fault-tolerant adder.
Simulation result of fault-tolerant QCA adder.
In QCA manufacturing, defects can occur during the synthesis and deposition phases, although defects are most likely to take place during the deposition phase [
In the proposed work, the QCA layout of the FTRA gate is converted into the corresponding hardware description language notations using the HDLQ Verilog library [
HDLQ modelling of QCA-based fault-tolerant adder.
Testing of the FTRA gate generated 78 unique fault patterns at the output, as shown in Table
Fault pattern of proposed fault-tolerant adder.
Input |
Output |
Fault pattern | Success rate | FT% | ||||||||||
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1 | 2 | 3 |
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43 | 44 | 45 |
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76 | 77 | 78 | ||||
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32/78 | 41.02 |
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34/78 | 43.59 |
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38/78 | 48.72 |
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38/78 | 48.72 |
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37/78 | 47.43 |
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39/78 | 50.00 |
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40/78 | 51.28 |
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41/78 | 52.56 |
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42/78 | 53.78 |
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Average FT = fault tolerance | 47.38 |
This work presents a novel architecture of fault-tolerant reversible adder (FTRA) gate. Experimental results establish the fact that the proposed FTRA achieved significant improvements in reversible circuits over the existing ones. A reversible arithmetic logic unit is synthesized based on the FTRA proposed. This is first attempt to synthesize a fault-tolerant full adder/subtractor using only single reversible logic block (FTRA) with optimal quantum cost to avoid wire-crossing bottleneck. Also, the application of this fault-tolerant logic in QCA nanotechnology gets an extra advantage in fault-tolerant computing with effective 47.38% fault-free output in the presence of all possible single missing/additional cell defects.
Though, the clocking structure beneath the QCA cell layer is also very important and nontrivial research issue.
The authors would like to thank Mr. Samik Some, UG student of CSE department, NIT Durgapur, for his valuable help in testing the design using HDLQ tool.