A Novel Reconfigurable MB-OFDM UWB LNA Using Programmable Current Reuse

This paper presents a design of a reconfigurable low noise amplifier (LNA) for multiband orthogonal frequency division multiplexing (MB-OFDM) ultra wideband (UWB) receivers. The proposed design is divided into three stages; the first one is a common gate (CG) topology to provide the input matching over a wideband.The second stage is a programmable circuit to control the mode of operation. The third stage is a current reuse topology to improve the gain, flatness and consume lower power. The proposed LNA is designed using 0.18μm CMOS technology. This LNA has been designed to operate in two subbands of MBOFDMUWB, UWBmode-1 and mode-3, as a single or concurrent mode.The simulation results exhibit the power gain up to 17.35, 18, and 11 dB for mode-1, mode-3, and concurrent mode, respectively. The NF is 3.5, 3.9, and 6.5 and the input return loss is better than −12, −13.57, and −11 dB over mode-1, mode-3, and concurrent mode, respectively. This design consumes 4mW supplied from 1.2 V.


Introduction
Ultra wideband (UWB) has many advantages over narrowband technology such as high data rate, low power, low complexity, and low cost technology. When The US Federal Communication Commission (FCC) recognized the potential advantages of UWB, it issued a report that allows UWB use for commercial communication systems in 2002, and its applications can operate in the unlicensed spectrum of 3.1-10.6 GHz [1]. UWB supports carrierless baseband signals such as impulse-radio IR-UWB, and it supports wideband with carrier such as multiband orthogonal frequency division multiplexing MB-OFDM UWB [2]. In MB-OFDM UWB systems, the spectrum from 3.1 to 10.6 GHz is divided into 14 subbands of 528 MHz as shown in Figure 1, which supports data rates from 53 to 480 Mbps [3,4].
In order to roam across different subbands, devices that support multinetwork applications are required. There is a strong motivation on using single chip supports multiband and multiapplications, due to it provides wireless access for users anywhere and anytime. In such reconfigurable devices, the design of low noise amplifier (LNA) is a critical issue because its has effects in the overall system and requirements as high gain, low noise figure (NF), and lower power consumption, with good input and output matching over each band of interest.
Recently, there are some schemes proposed to the multistandard LNAs like parallel, concurrent, wideband, and reconfigurable LNA. The first approach is the parallel architecture that emploies multiple architectures for each band of interest [5]. However, this approach requires large area, different design for each band, and more time. The concurrent and wideband approaches provide multiband simultaneously [6] by providing the input matching, but this approaches pass the large interference the matching network; therefore, increasing the linearity is required [7,8]. Recently, the reconfigurable approach presents to discrete band and/or concurrent bands [7] to solve the tradeoff between area, power, and cost. Many approaches present a continuous tuning like [8,9]; it is good for narrowband applications, but it is not applicable for widebands. This paper proposed a new reconfigurable MB-OFDM LNA for UWB systems. The proposed LNA reconfigured over dual widebands and it works as a discrete band or concurrent   based on the programmable part. This design based on CG topology to provide the input matching over wideband [10,11], current reuse technique shown in Figure 2 used to provide high and flat gain, and low power consumption [12][13][14], and programmable circuit to select the band of operation. This paper is organized as follows, the demonstration of the proposed circuit, defect and solution of current reuse technique will be presented in Section 2. Section 3 discusses the simulation results of the proposed LNA. Finally, the conclusion is presented in Section 4.

Circuit Design of the Proposed Reconfigurable MB-OFDM UWB LNA
The proposed LNA was designed by a standard 0.18 m CMOS process. Figure 3(a) shows the schematic of the LNA. This circuit consists of three stages distinguished by three different blocks in Figure 3(a). The first one, input matching stage in block-1 in Figure 3(a), the CG topology used to control the input matching over wideband [11,15] where the input impedance at resonated with the gate-to-source parasitic capacitance of 1 of 1 is in = 1/ 1 , where 1 is the transconductance of transistor 1 . Therefore, the matching bandwidth can be calculated by Second stage is the programmable switches in block-2 in Figure 3(a), actually this stage is proposed to achieve two main tasks. The first task is used to select the branch that will provide the desired band, consequently, the selected band depends on Table 1, where 0 is the center frequency of the selected mode. The other task is used to solve current reuse defect, without using this stage the control of this circuit can be made by transistor 2 and 2 , but when one of them is OFF, 1 and 2 nodes will be shorted, thereby the overall circuit performance will be effected.
To solve this problem the programmable circuit is proposed, when transistor 2 is OFF as shown in Figure 3(b) 1 and 2 nodes will be disconnected.
Finally, the current reuse stage in block-3 in Figure 3(a), is used to achieve high and flat gain, and lower power consumption. This architecture was simplified in Figure 2 and it consists of series inductor 1 and shunt capacitor 1 connected to DC cascode transistors 1 and 2 . 1 is used to resonate with gate-to-source parasitic capacitance of 2 , 2 , while 1 is selected large in the desired bandwidth to provide high impedance path to block RF signal. Furthermore, when the capacitance is selected large, the transistors 1 and 2 act as two common source (CS) cascaded stage at high frequency [12][13][14].

Simulation Results
Design of the proposed reconfigurable MB-OFDM UWB LNA was carried out using Spectre simulator from Cadence Design Suite. The proposed circuit consumes 3.32 mA from 1.2 V supply when it works in single mode, but when it works in concurrent mode it consumes 3.39 mA. The simulation results for S-parameters and NF are illustrated in Figure 4 and Figure 5. 11 is less than −12, −13.57, and −11 dB for UWB mode-1 with center frequency 3.432 GHz, UWB mode-3 with center frequency 4.488 GHz, and concurrent mode with center frequency 3.96 GHz, respectively. These results depict the input matching network of the proposed LNA under −10 dB, the reason behind this due to CG topology and selection of appropriate value of to resonate with 1 , so the proposed design has a good input matching. Figure 4(b) presents the reverse isolation 12 between output and input ports over bands of interest, where it is less than −50.5, −44.2, and −52 dB for mode-1, mode-3, and concurrent mode, respectively. Also the better isolation comes from CG topology, where the input isolated from the output of this topology. Figure 4(c) illustrates the voltage gain 21 of the proposed LNA. As depicted, the proposed LNA achieves 17.35, 18, and 11 dB for mode-1, mode-3, and concurrent mode, respectively. The high gain of this LNA is due to current reuse, where the overall transconductance of this design is = 1 2 . However, the gain of concurrent mode is lower than single mode, due to the parallel resistance of branches (output resistance of 2 , 2 series with output resistance of 1 , and 1 are parallel with output resistance of 2 , 2 series with output resistance of 2 , and 2 ). Figure 4(d) shows the output return loss 22 of the reconfigurable LNA where it is under −14.9, −9.6, and −14.2 dB for all modes.
The good output matching was achieved due to the selection of appropriate values for output matching network ( 2 , 2 , 2 , out , out , and ). The simulated NF versus bands of interest is shown in Figure 5. As noticed, NF of the proposed LNA achieves 3.49-3.53, 3.9-3.93, and 6.29-6.8 dB for mode-1, mode-3, and concurrent mode, respectively. The high NF of concurrent mode is due to the number of transistors that are used in this mode.
The performance of the proposed LNA and a comparison with existing architectures are summarized in Table 2. As shown in this table, the proposed LNA provides discrete tuning and concurrent, while the existing techniques either provide discrete, concurrent, or continuous tuning. The voltage gain 21 for the proposed architecture is lower than [8,9,16], because they use the cascode and cascade topologies for that they consume higher power when compared with the proposed reconfigurable LNA.   and the noise performance of this circuit was presented. The proposed LNA operates by 1.2 V supply and consumes 3.32 mA for single mode (UWB mode-1 or mode-3) and 3.39 mA for concurrent mode. Finally, it has been designed by 0.18 m CMOS process.