International Scholarly Research Notices
Volume 2014 (2014), Article ID 145759, 6 pages
http://dx.doi.org/10.1155/2014/145759

Research Article

Aspect Ratio Model for Radiation-Tolerant Dummy Gate-Assisted n-MOSFET Layout

Min Su Lee and Hee Chul Lee

Division of Electrical Engineering, School of Electrical Engineering & Computer Science, Korea Advanced Institute of Science and Technology, 373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701, Republic of Korea

Received 27 March 2014; Accepted 29 October 2014; Published 18 November 2014

Academic Editor: Giuseppe Biondi-Zoccai

Copyright © 2014 Min Su Lee and Hee Chul Lee. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

In order to acquire radiation-tolerant characteristics in integrated circuits, a dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout was adopted. The DGA n-MOSFET has a different channel shape compared with the standard n-MOSFET. The standard n-MOSFET has a rectangular channel shape, whereas the DGA n-MOSFET has an extended rectangular shape at the edge of the source and drain, which affects its aspect ratio. In order to increase its practical use, a new aspect ratio model is proposed for the DGA n-MOSFET and this model is evaluated through three-dimensional simulations and measurements of the fabricated devices. The proposed aspect ratio model for the DGA n-MOSFET exhibits good agreement with the simulation and measurement results.

1. Introduction

According to a recent report [1], the dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout, as shown in Figure 1(a), has radiation-tolerant characteristics with regard to a total ionizing dose up to 500 krad (Si). The DGA n-MOSFET layout eliminated all possible radiation-induced leakage currents through the isolation of the source and drain from the sidewall oxides using dummy gates and P-active layers involving p+ layers. In the DGA n-MOSFET, the isolation of the source and drain from the sidewall oxides results in a different channel shape compared with that of the standard n-MOSFET.

(a) DGA n-MOSFET layout

(b) Standard n-MOSFET layout

Figure 1: (a) DGA n-MOSFET layout and (b) standard n-MOSFET layout.

The standard n-MOSFET, which is shown in Figure 1(b), has a channel region with a rectangular shape, which has a width and length . Furthermore, this simple geometry enables easy calculation of its aspect ratio. The current density of the standard n-MOSFET is constant along its length [2]. Therefore, the aspect ratio of the standard n-MOSFET is calculated through dividing by . When the integrated circuit is designed using standard MOSFETs, the circuit characteristics are determined using adjustments of each aspect ratio of in the MOSFETs. Circuit designers can adjust only the aspect ratios in order to obtain specified circuit characteristics because the other parameters are determined in the device fabrication process. Therefore, the aspect ratio of the MOSFET is the most important parameter in the circuit design.

The channel shape of the DGA n-MOSFET is presented in Figure 2 with the removal of the areas other than the channel area. Its current density is not constant along its length due to its inherent structure shape. Therefore, the aspect ratio of the DGA n-MOSFET cannot be obtained in the same manner as a standard n-MOSFET. As a result, a specified aspect ratio model for the DGA n-MOSFET should be developed.

Figure 2: The channel region in the DGA n-MOSFET layout. The channel of the DGA n-MOSFET layout has an extended channel area at the edge of the source and drain compared with the standard n-MOSFET. , , and are the channel length, channel width, and extended width, respectively.

According to previous reports [3, 4], the resistance, which has a shape similar to the channel region of the DGA n-MOSFET, does not have an analytical solution. Therefore, several alternative formulas have been reported and evaluated through the adoption of approximations. However, these formulas have very high complexity and difficulty to be adopted for the DGA n-MOSFET. Furthermore, the specified aspect ratio model for the DGA n-MOSFET has not been developed yet.

For the practical use of the DGA n-MOSFET in circuit design, this study proposes a simple aspect ratio model by adopting several reasonable approximations. It is expected that the proposed simple aspect ratio model simplifies the estimation of the aspect ratio of the DGA n-MOSFET. The proposed aspect ratio model is evaluated using a three-dimensional simulation with the SILVACO ATLAS simulation tool. Furthermore, the proposed aspect ratio model is also evaluated through device fabrication and its measurement.

2. Proposed Aspect Ratio Model

2.1. Aspect Ratio Model for the Trapezoidal Structure

Figure 3 shows the trapezoidal structure with its parameters. The aspect ratio of the trapezoidal structure was modeled from an approximated triode region drain current based on the gradual channel approximation and charge sheet assumption [2]. The effective aspect ratio of the trapezoidal structure can be calculated using the following equation:

where , , and   are the channel length, half of the source side channel width, and corner angle, respectively [2].

Figure 3: The transistor with a trapezoidal channel shape. , , and   are the channel length, half of the source side channel width, and corner angle, respectively.

2.2. Aspect Ratio Model for the DGA n-MOSFET

The channel region of the DGA n-MOSFET is approximated using the series association of two trapezoidal transistors. Moreover, the value of the corner angle was specified in order to determine whether to place an additional rectangle between the two trapezoid transistors. Thus, it was determined that if , a rectangle is added between the two trapezoid transistors. , , and are the channel length, extended width, and corner angle, respectively. This approximation was developed based on two assumptions. The first assumption is that the current density at the corner regions of the DGA n-MOSFET channel can be negligible. It is intuitively known that the electric field will not reach the corner regions; consequently, the series association of the two trapezoidal structures substitutes the DGA n-MOSFET channel region. The second assumption is that the corner angle of the substituted trapezoid structure will be constant regardless of the length , extended width , and width , because the spreading angle of the current at the edge of the source is expected to be constant. The behavior of the current spreading is determined by the contact shape between the electrodes and channel region. In the DGA n-MOSFET, the source and drain edges are always positioned in the middle of the upper and lower sides of the channel region.

The final approximated channel shapes are presented in Figure 4. In Figures 4(a) to 4(c), the width , extended width , and corner angle have the same values; however, the length has different values and it increases in order of the figure number. Figure 4(a) presents the case with the condition of .

(a) When

(b) When

(c) When

Figure 4: Approximated channel shapes of the DGA n-MOSFET: (a) when , (b) when , and (c) when . , , , and are the channel length, channel width, extended width, and corner angle, respectively.

In this case, the series association of the two trapezoidal transistors replaces the channel area of the DGA n-MOSFET. Moreover, a space exists between the bottom vertexes of the upper trapezoid and both left and right sides of the original channel area. The effective aspect ratio for the approximated structure shown in Figure 4(a) is calculated using the following equation:

where , , and   are the channel length, channel width, and corner angle, respectively.

Figure 4(b) represents the case when the condition is . In this case, the series association of the two trapezoidal transistors also replaces the channel area of the DGA n-MOSFET. However, the bottom vertexes of the upper trapezoid encounter both left and right sides of the original channel area. The effective aspect ratio for the approximated structure shown in Figure 4(b) is calculated using the following equation:

where , , and   are the channel length, channel width, and corner angle, respectively.

Figure 4(c) represents the case when the condition is . In this case, the series association of the two trapezoidal transistors and one rectangle replaces the channel area of the DGA n-MOSFET. The rectangle is added between the two trapezoidal structures. The effective aspect ratio for the approximated structure shown in Figure 4(c) is calculated using the following equations:

where , , , and   are the channel length, channel width, extended width, and corner angle, respectively. Moreover, and indicate the aspect ratio formula for the trapezoidal structure and rectangle, respectively, as shown in Figure 4(c).

3. Simulation Results

3.1. Evaluation of Current Density

The standard n-MOSFET structure and DGA n-MOSFET structure were designed to be compatible with the commercial 0.35 μm process technology using the SILVACO ATLAS simulation tool. For both the standard and DGA n-MOSFETs, the gate oxide thickness, body thickness, and body doping density were 7 nm, 6 μm, and 8e16 #/cm³, respectively. For the DGA n-MOSFET, the side p+ doping density was 1e19 #/cm³. Moreover, the isolation structure was adapted using local oxidation of silicon (LOCOS). Five different widths (2 μm, 5 μm, 8 μm, 10 μm, and 12 μm) and three different lengths (0.5 μm, 1 μm, and 3 μm), which resulted in fifteen different structures, were simulated. For the DGA n-MOSFET, the extended width was fixed to 2 μm.

Figure 5 presents the current density of the DGA n-MOSFETs at the channel surface when the gate, source, drain, and body voltages were 3.3 V, 0 V, 0.05 V, and 0 V, respectively. In Figures 5(a) to 5(c), both the width and extended width were 2 μm. The length increased in order of the figure number as 0.5 μm, 1 μm, and 3 μm. In order to evaluate the proposed effective aspect ratio model for the DGA n-MOSFET, the current densities are presented using rainbow colors in a linear scale relative to each maximum current density. From Figure 5, it can be seen that the currents increasingly expanded to the extended channel area as the channel length increased.

(a)

(b)

(c)

Figure 5: Simulated current density of the DGA n-MOSFETs at the channel surface when the gate, source, drain, and body voltages are 3.3 V, 0 V, 0.05 V, and 0 V, respectively. Current densities are presented using rainbow colors relative to its maximum current density. All and are 2 μm; increases in order of the figure number as follows: (a) 0.5 μm, (b) 1 μm, and (c) 3 μm. The white dashed lines indicate the approximated channel area when   is 0.977.

The corner angle   was determined using comparisons of the proposed effective aspect ratio model with the simulation results. When the corner angle   was 0.977, the proposed effective aspect ratio model had the best agreement with the simulation results. The approximated channel area with a corner angle   of 0.977 is indicated in Figure 5 using the white dashed lines. These white dashed lines also agree well with the current density profile.

3.2. Extracted Effective Aspect Ratio of the DGA n-MOSFET

In the simulation, the effective aspect ratios for the DGA n-MOSFETs were extracted using the following equations:

where ,  ,  ,  , , , and   are the drawn width, effective width, drawn length, effective length, electron mobility, gate oxide capacitance per unit area, and channel length modulation parameter, respectively. Moreover, the superscripts “DGA” and “STD” refer to the DGA n-MOSFET and standard n-MOSFET, respectively. When calculating the effective aspect ratios, it was assumed that the DGA n-MOSFET and standard n-MOSFET have the same electrical parameters for the and channel length modulation parameter  . The transconductance was adopted at a of 0.05 V in order to minimize the effects induced by the channel length modulation parameter   difference between the DGA n-MOSFET and standard n-MOSFET. Furthermore, the transconductance was used at a of 1.5 V in order to use a saturated .

Moreover, in order to acquire the effective width and effective length , the and were extracted from the simulation results of the standard n-MOSFETs. From the simulation results, the extracted and were 0.05 μm and 0.005 μm, respectively.

Figure 6 shows the calculated aspect ratios using the proposed aspect ratio model and the extracted aspect ratios from the simulation results. The errors of the proposed effective aspect ratio model compared with those of the simulation results were contained between −0.4% and 1.4%. The proposed effective aspect ratio model was well matched with the simulation results.

Figure 6: Comparison of the effective aspect ratios of the DGA n-MOSFETs when calculated using the proposed effective aspect ratio model and when extracted from the three-dimensional simulation.

4. Experimental Results

The standard n-MOSFET and DGA n-MOSFET were fabricated using the MagnaChip and Hynix 0.35 μm technology with a gate oxide thickness of 7.3 nm and LOCOS for the isolation of the active areas. Three different widths (5 μm, 8 μm, and 12 μm) and three different lengths (0.5 μm, 1 μm, and 3 μm), which resulted in a total of nine structures, were fabricated. For the DGA n-MOSFET, the extended side channel width was fixed to 2 μm.

The fabricated devices were measured using an Agilent 4156A semiconductor parameter analyzer. The - curves were measured and were then differentiated by in order to acquire the transconductance curve. When measuring the - curves, the was set to 0.05 V. Moreover, all transconductance values used to extract the aspect ratios were chosen at a of 1.5 V.

As in the simulation case, in order to extract the effective aspect ratios for the DGA n-MOSFETs, (5) were also adopted. Moreover, from the measurement results, the extracted and were 0.15 μm and 0.05 μm, respectively.

Figure 7 shows the calculated aspect ratios using the proposed aspect ratio model and the extracted aspect ratios from the measurement results. The errors of the proposed effective aspect ratio model compared with the measurement results were contained between −3% and 5.4%. When considering the process variation, which was ±5%, the error range is acceptable. Therefore, the proposed effective aspect ratio model was well matched with the measurement results.

Figure 7: Comparison of the effective aspect ratios of the DGA n-MOSFETs when calculated using the proposed effective aspect ratio model and when extracted from the measurement.

5. Conclusion

For practical use of the radiation-tolerant DGA n-MOSFET in designing a radiation-tolerant integrated circuit, an effective aspect ratio model of the DGA n-MOSFET was proposed. In the proposed effective aspect ratio model, the channel area of the DGA n-MOSFET was approximated using a trapezoidal structure and a rectangular structure. When , the rectangular structure was added between the two trapezoidal structures.

The proposed effective aspect ratio model was evaluated using a three-dimensional simulation and through measurement of the fabricated devices. Compared with the simulation results, the proposed effective aspect ratio model had an error range between −0.4% and 1.4%. Moreover, compared with the measurement results, the proposed effective aspect ratio model had an error range between −3% and 5.4%. Therefore, it can be concluded that the proposed effective aspect ratio model is well matched with the simulation and measurement results.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgments

The authors thank Dr. Nam Ho Lee and Dr. Hyun Jin Lee at the Korea Atomic Energy Research Institute as well as Dr. Kwang Sun Ryu at the Satellite Technology Research Center at Korea Advanced Institute of Science and Technology (KAIST) for their helpful comments. This work was supported by a project of the Ministry of Education, Science and Technology (Development of Radiation Hardening Design Technology of MOSFET, ADC, and SRAM for Satellites) and the IC Design Education Center in Korea Advanced Institute of Science and Technology.

References

M. S. Lee and H. C. Lee, “Dummy gate-assisted n-MOSFET layout for a radiation-tolerant integrated circuit,” IEEE Transactions on Nuclear Science, vol. 60, no. 4, pp. 3084–3091, 2013.

R. Giacomini and J. A. Martino, “Modeling silicon on insulator MOS transistors with nonrectangular-gate layouts,” Journal of the Electrochemical Society, vol. 153, no. 3, pp. G218–G222, 2006.

S. Karmalkar, P. V. Mohan, H. P. Nair, and R. Yeluri, “Compact models of spreading resistances for electrical/thermal design of devices and ICs,” IEEE Transactions on Electron Devices, vol. 54, no. 7, pp. 1734–1743, 2007.

Y. S. Muzychka, J. R. Culham, and M. M. Yovanovich, “Thermal spreading resistance of eccentric heat sources on rectangular flux channels,” Journal of Electronic Packaging, vol. 125, no. 2, pp. 178–185, 2003.