A new and simple but effective electromagnetic interference suppression technique based on field programmable logic array (FPGA) technology to provide a significant EMI noise attenuation in DC-DC converters is discussed. The voltage controlled boost converter for EMI reduction is analyzed using FFT under traditional PWM technique and chaotic mode operation. This technique aids the DC-DC converters to comply in specified EMI limits and replace conventional bulky passive filter with a simple passive filter. A prototype model has been tested and hardware results show significant reduction of EMI in chaotic mode operation of the boost converter.

Electromagnetic iterference is a man-made or natural electromagnetic disturbance signal which results in unacceptable response and sometimes in malfunctioning of an electrical or electronic device. So it is essential to suppress the EMI at switching. Though there are organizations such as IEC, IEEE, and FCC that are consistently insisting on EMC standards for different environments, the increasing essentiality of DC-DC converter in different applications [

The EMI filters are traditionally used in power converters to attenuate switching noise and to meet the EMI standards for many years now. However, the bulkiness, design limitation for a band of frequency, parasitic reactive elements, and chance of attenuating the useful signal lead to some other effective alternatives like soft switching and random modulation techniques. However, soft switching has some limitations because of its auxiliary circuits. But incorporation of chaotic modulation, a type of random modulation method, is effective in suppression of EMI for a wider range of frequency.

Over the years, EMI filters are widely used in power electronics systems for EMI noise suppression [

Though there are lots of techniques, such as EMI filter and shielding, for mitigation of EMI, they work as a remedy after EMI is generated [

FPGAs—field programmable gate arrays [

By combining the advantages of EMI filtering with chaotic PWM switching, it is possible to achieve effective spectral peak reduction in the network. Hence, in this paper, the objective of effective EMI suppression is realized by incorporating the technique by this novel combination. First, the simulations of conventional PWM technique and chaotic switching are done. Then the hardware prototype of passive filter [

The organization of this paper is as follows. Section

Figure

EMI Coupling path in ideal AC-DC power supply.

Power electronic circuits are typical examples of variable structure systems where the topology is changed due to the operation of the switching element. As a result, systems become nonlinear and time varying. Although DC-DC converters are well known for their significant advancement in power density and their low thermal dissipation, threat of generating EMI by

DC-DC converter sheds electromagnetic emissions and thus forms the main source of EMI. Therefore, controlling EMI in a DC-DC converter is of great importance for cleaning the entire EMI environment. Of all types of DC-DC converters, boost converters are widely adopted and its general circuit diagram is shown in Figure

Basic topology of boost converter with chaotic PWM.

Block diagram for the proposed method.

The elaborated circuit diagram of the proposed methodology is shown in Figure

Circuit diagram for the proposed method.

The LISN is stabilizing the impedance of the source and the circuit for the accurate measurement of conducted EMI generated in the boost converter. The techniques are combined for the effective reduction of the EMI as discussed earlier.

EMI Filters are widely used in power electronic systems for EMI noise suppression. Conventional passive EMI filters are either one-or two-stage LC filters. EMI filters are usually composed of common mode (CM) and differential mode (DM) filters. CM filters are used to suppress CM noise, which flows through the parasitic capacitance between the power electronics systems, ground, line impedance stabilization network (LISN), and the power lines. The capacitance of common mode (CM) filter is usually limited by the safety standard-IEC60950-1. As a result, the total CM capacitance cannot be too large. Hence, to achieve the low cutoff frequency to achieve high attenuation on CM noise, the CM inductance in CM filters is usually very large. The inductors and capacitors in EMI filters are not ideal components. Firstly, they are self-parasitic [

(a) General equivalent circuit of CM noise with filter. (b) Schematic of CM filter and CM noise source.

The common mode noise is considered with high source but low load impedances and, according to the impedance mismatch criteria for EMI filter design, a Γ-shaped filter (CL topology) should be incorporated for CM noise suppression, where the capacitor is faced with an inverter and the CM choke is faced with a line impedance stabilization network (LISN). However, due to the effect of stray winding capacitance, the CM choke is no longer with an inductance property after its self-resonant frequency. In order to pay off the filtration performance degradation caused by the parasitic winding capacitance of the CM choke, another capacitor is connected on the LISN side; thus, a

The common mode filter is designed as follows. The attenuation amplitude is shown in (

The common-mode voltage measured across the LISN with the common-mode filter can be therefore derived as

For the output voltage 24 V and the load current of 0.2423 A, the output impedance calculated is 99.05 ohms. The filter capacitor and inductor that could be calculated from the formula (

Pulse width modulation technique is generally used for generating the pulses required for switching operation in the DC-DC converter. In PWM, the carrier wave will be a chaotic carrier wave and the modulating signal remains the same, that is, DC signal. The frequency of the carrier wave determines the frequency of the PWM pulses; since the carrier wave is chaotic in nature [

PWM technique is generally used for generating the pulses required for the switches of the DC-DC converter. Here, for the PWM, the carrier wave is chaotic in nature and the modulating signal remains the same, that is, DC signal [

Randomization parameters in switching signal.

In Figure

Among the different randomized carrier frequency techniques, the RCFMFD is chosen because of its simplicity and characteristics of giving a constant output voltage for the DC-DC converter. In this scheme, the carrier frequency is randomized maintaining the duty ratio constant. This switching frequency of the random switching techniques has its own limitation such as increasing randomization range of the switching frequency increases the noise reduction until a certain ratio, after which the noise reduction again starts to decrease. The later may be due to the increased low-frequency noise and the overlaps between the successive frequency spectrum ranges. To avoid such overlapping, a superior limit of the randomization range of the switching frequency should not be taken more than ± one-third of the central switching frequency. The improved performance and cost reduction of FPGA technology have made it applicable for power supply application in DC- DC Converters.

In order to investigate the effectiveness of the stochastic variable randomness level on spreading harmonic power, a randomness level

Pseudorandom number is assimilated to make the PWM period random, which can be generated using a linear feedback shift register (LFSR). A LFSR is a shift register; when clocked, it advances the signal through the register from one bit to the next Most Significant Bit. Some of the outputs are combined in XOR configuration to form a feedback mechanism. A linear feedback shift register can be formed by performing XOR on the outputs of two or more of the flip-flops together and feeding those outputs back into the input of one of the flip-flops as shown in Figure

12-bit linear feedback shift register.

When the outputs of the flip-flops are loaded with a seed value (anything except all 0’s, which would cause the LFSR to produce all 0 patterns) and the LFSR is clocked, a pseudorandom pattern of 1’s and 0’s is generated. Note that the only signal necessary to generate the test patterns is the clock. LFSR produces the maximum number of (

The boost converter tested for conducted noise has a single switch and therefore requires a single PWM signal of central frequency of 100 kHz. Pulse width modulation signals are generated using a Xilinx Spartan-3E LX45 FPGA board, which has a clock frequency of 50 MHz; the logic used here for pulse generation is counting the clock frequency:

The randomization technique used for generation of chaotic PWM pulse is RCFMFD. The algorithm can be written as follows.

Initialize the PWM period value and count value and instantiate the LFSR module.

Always when a positive edge of clock occurs, do the following steps.

Calculate the ON time for the PWM signal based on required duty cycle and PWM period value.

Initially begin with ON pulse increment count with 1 on each positive edge of clock till count reaches ONtime. Now make PWM pulse OFF, increment count with 1 on each positive edge of clock till count value reaches the PWM period value.

When the count value exceeds the PWM period value, reinitialize count with 1 and calculate the next PWM period value by adding LFSR output value with a fixed value corresponding to the maximum frequency.

And also it can be represented through flowchart shown in Figure

Flowchart for RCFMFD-based chaotic PWM generation.

The various cases like PWM without and with filter and chaotic switching without and with filter are simulated in MATLAB/SIMULINK. The FFT of the common-mode output voltages is obtained. Figures

(a) FFT of output voltage without EMI filter for periodic pulses. (b) FFT of output voltage without EMI filter for chaotic pulses.

(a) FFT of output voltage with EMI filter for periodic pulses. (b) FFT of output voltage with EMI filter for chaotic pulses.

In order to verify the effectiveness of the proposed algorithm a hardware prototype with the specification mentioned in Table

Spectral peak magnitude for different methods.

Method | Multiplier | Instants | |||
---|---|---|---|---|---|

13 ns | 16.5 ns | 20 ns | 27.5 ns | ||

Periodic without filter | 7.3/3.2 | 2.7 | 1.82 | 0.69 | −0.912 |

Chaotic without filter | 5.3/3.1 | 0.85 | 0.25 | −1.02 | −2.04 |

Periodic with filter | 5.8/3.1 | 1.31 | 1.12 | −0.19 | −1.87 |

Chaotic with filter | 3.3/3.1 | 0.11 | −0.21 | −1.06 | −1.59 |

The programming and interfacing are done by Xilinx Spartan-3E XC3S500E FPGA board associated with Xilinx ISE Design Suite 13.1_2. The chaotic PWM pulses that are generated using Xilinx Spartan-3E XC3S500E FPGA are fed to the designed prototype boost converter to analyze and investigate the effect of randomization of carrier wave in reducing the conducted noise. The Xilinx Spartan-3E XC3S500E FPGA board has an oscillator frequency of 50 MHz and gives an output voltage of 3.3 V. This voltage is not sufficient enough to drive the switching device MOSFET IRF 540; therefore an amplifier and Opto-coupler circuit are being employed for making the gate pulses to 10 V.

The generated periodic and RCFMFD PWM pulses are shown in Figures

Hardware setup.

(a) Periodic PWM pulse of 100 kHz. (b) CPWM pulses in the range

FFT of output voltage without EMI filter for (a) periodic pulses and (b) chaotic pulses.

FFT of output voltage with EMI filter for (a) periodic pulses and (b) chaotic pulses.

Comparison of spectral peak magnitude.

The effect of FPGA-based chaotic PWM technique using RCFMFD spread spectrum scheme along with EMI filter on the conducted noise characteristics of a DC-DC converter (boost converter) has been experimentally investigated. The FFT analysis shows that the spectral peaks are reduced drastically in chaotic modulation using filter. The chaotic modulation is also more effective compared to PWM with and without filter. From Table

Inductor

Capacitor

Load resistor

Power switch

Power diode

Input voltage

Output voltage

Switching time period

Duration of the

Duration of the ON state within this cycle

Delay form the beginning of the switching cycle to the turn-on within the cycle

The switching function

Time at which

Switching Frequency.

Electromagnetic Interference

Electromagnetic Compatibility

Fieldprogrammable gate array

Pulse width modulation

Chaotic pulse width modulation

Printed circuit board

Linear feedback shift register

Power spectral density

Randomized carrier frequency modulation with fixed duty ratio

Line impedance stabilization network

Equivalent series inductance

Equivalent parallel capacitance.

The authors declare that there is no conflict of interests regarding the publication of this paper.

This work was supported by Power Electronics and Drives Division, School of Electrical Engineering, VIT University, Vellore, India.