A novel quantization error (QE) compensation method is proposed in design of high accuracy fixed-width radix-4 Booth multipliers, which will effectively reduce the QE and save the area of multipliers when they are employed in cognitive radio (CR) detector and digital signal processor (DSP). The truncated partial-products of the proposed multipliers are finely divided into three sections: reserved section, adaptive compensation section, and constant compensation section. The QE compensation carries of the multipliers are generated by applying probability estimation based on a shrunken minor truncated section which is a combination of the constant compensation and adaptive compensation. The proposed compensation method not only reduces the QE of the fixed-width Booth multipliers, but also avoids the exhaustive computing resources (time and memory) during getting the compensation carries by statistical simulation. The proposed method can achieve higher accuracy than the existing works under the same area and power budgets. Simulation and experiment results show that the improved compensation method has the minimum power-delay products compared with the existing methods under the same area and can save up to 30% area for realization of full-width radix-4 Booth multipliers.
The fixed-width multipliers have been widely used in the design of digital signal processor (DSP) due to their smaller area and lower power dissipation [
The traditional methods of QEC for fixed-width multipliers can be divided into three categories. The first category is constant compensation [
The compensation carries of the minor truncated section in [
Based on the trade-off between the accuracy and computer resources, the minor truncated section is divided into two parts in this paper: the lower partial-products and the upper partial-products. In fact, the compensation carries are less affected by the lower partial-products of the minor truncated section. Therefore, we propose that a compensation constant of the lower partial-products can be generated by statistical analysis, and then the compensation constant is incorporated into the upper partial-products to form a shrunken minor truncated section. Finally, the quantitative compensation carries are created by applying probability estimation based on the shrunken minor truncated section; hereafter, this multiplier is called shrunken partial-products compensation (SPPC) Booth multiplier. The proposed QEC method not only reduces the QE of the multipliers, but also avoids the exhaustive simulation resource requirements. Simulations and experiments show that, comparing with the previous works [
The rest of the paper is organized as follows. Section
The modified radix-4 Booth recoding method was proposed in [
The
According to modified radix-4 Booth recoding, from the most significant bit (MSB), every three bits form a group and adjacent groups overlap by one bit. When
The recoding radix upon (
The modified Booth recoding.
|
|
|
|
|
|
---|---|---|---|---|---|
000 | 0 | 0 | 0 | 0 | 0 |
001 | ×1 | 0 | 1 | 0 | 1 |
010 | ×1 | 0 | 1 | 0 | 1 |
011 | ×2 | 1 | 0 | 0 | 1 |
100 | ×(−2) | 1 | 0 | 1 | 1 |
101 | ×(−1) | 0 | 1 | 1 | 1 |
110 | ×(−1) | 0 | 1 | 1 | 1 |
111 | 0 | 0 | 0 | 1 | 0 |
Scheme of modified radix-4 Booth recoding.
In a radix-4 Booth multiplier, each partial-product
Partial-products and multiplicands (
|
|
|
|
|
---|---|---|---|---|
000 | 0 | 0 | 0 | 0 |
001 | 0 | 0 | 1 | 1 |
010 | 0 | 0 | 1 | 1 |
011 | 0 | 1 | 0 | 1 |
100 | 1 | 0 | 1 | 0 |
101 | 1 | 1 | 0 | 0 |
110 | 1 | 1 | 0 | 0 |
111 | 1 | 1 | 1 | 1 |
A
Partial-products of different
|
|
|
|
|
|
|
|
|
---|---|---|---|---|---|---|---|---|
0 |
|
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
|
0 |
−1 |
|
|
|
|
|
|
|
1 |
2 |
|
|
|
|
|
|
|
0 |
−2 |
|
|
|
|
|
|
|
1 |
Partial-product array of radix-4 Booth multiplier (with
The partial-products of modified Booth multipliers can be divided into two sections: reserved section
Assuming that a decimal point is between
In the proposed method, the QE of
In Table
Supposing that both the probabilities of
Based on the above proposed SPPC multiplier, the
Rebuilt shrunken adaptive section.
The maximum carries will be generated if all
According to the number of 1 in
The statistic of carry output states for different categories.
Category | Total numbers of |
NoS | ||||||
---|---|---|---|---|---|---|---|---|
|
|
|
|
|
|
| ||
cate-0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
cate-1 | 7 | 0 | 0 | 0 | 0 | 0 | 8 | |
cate-2 | 63 | 21 | 0 | 0 | 0 | 0 | 0 | 82 |
cate-3 | 511 | 350 | 35 | 0 | 0 | 0 | 0 | 83 |
cate-4 | 4095 | 3605 | 1225 | 35 | 0 | 0 | 0 | 84 |
cate-5 | 32767 | 31486 | 18844 | 2898 | 21 | 0 | 0 | 85 |
cate-6 | 262143 | 259147 | 205534 | 71022 | 4963 | 7 | 0 | 86 |
cate-7 | 2097151 | 2090724 | 1897019 | 1048576 | 200133 | 6428 | 1 | 87 |
cate-8 | 16777215 | 16764354 | 16144677 | 11782380 | 4146393 | 438834 | 6435 | 88 |
We then encode each category with 4-bits to associate
Relations between category code and
|
|
|
|
|
---|---|---|---|---|
0000 | 0 | 0 | 0 | 0 |
0001 | 1 | 0 | 0 | 0 |
0010 | 1 | 0 | 0 | 0 |
0011 | 1 | 1 | 0 | 0 |
0100 | 1 | 1 | 0 | 0 |
0101 | 1 | 1 | 1 | 0 |
0110 | 1 | 1 | 1 | 0 |
0111 | 1 | 1 | 1 | 1 |
1000 | 1 | 1 | 1 | 1 |
According to Table
The circuit implementation of category encoding is shown in Figure
Category encoding circuits.
In light of (
Carry generation circuits.
According to the above discussions, a modified radix-4 Booth fixed-width multiplier with the proposed QEC circuits is shown in Figure
Partial-product array of fixed-width Booth multiplier with proposed QEC.
The comparison of various errors between the proposed SPPC Booth multipliers and the ideal truncated Booth multiplier and other previous works is listed in Table
Comparisons of QE.
Width (bits) | Multiplier |
|
|
|
Sample ratios in QE values (%) | ||
---|---|---|---|---|---|---|---|
|
|
|
|||||
Ideal | 0.5 | 0 | 0.0833 | 100% | — | — | |
8 | [ |
1.1641 | 0.1768 | 0.1459 | 79.9 | 21.1 | 0 |
[ |
1.5000 | 0.1328 | 0.1664 | 77.2 | 22.797 | 0.0031 | |
[ |
1.1680 |
|
0.1367 | 81.5 | 18.5 | 0 | |
[ |
1.1680 | −0.1152 | 0.1237 | 87.7 | 12.3 | 0 | |
[ |
|
0.1534 |
|
|
|
0 | |
SPPC | 1.4308 | 0.0941 | 0.1365 | 90.3 | 9.698 | 0.0016 | |
|
|||||||
10 | [ |
1.3652 | 0.2028 | 0.1713 | 74.9 | 25.1 | 0 |
[ |
1.5000 | 0.1211 | 0.1713 | 74.0 | 22.558 | 0.0121 | |
[ |
1.5000 | − |
0.1542 | 77.43 | 22.57 | 0 | |
[ |
1.5000 | −0.1284 | 0.1379 | 80.28 | 19.72 | 0 | |
[ |
|
0.1637 |
|
|
|
0.009 | |
SPPC | 1.5525 | 0.1074 | 0.1417 | 89.9 | 10.08 | 0.0084 | |
|
|||||||
12 | [ |
1.5649 | 0.2203 | 0.1960 | 72.50 | 27.50 | 0 |
[ |
2.0000 | 0.1270 | 0.1950 | 73 | 26.65 | 0.018 | |
[ |
1.6667 |
|
0.1671 | 76.83 | 23.17 | 0 | |
[ |
1.6667 | −0.1229 | 0.1521 | 78.60 | 21.384 | 0.016 | |
[ |
|
0.1763 |
|
|
|
0.013 | |
SPPC | 1.6302 | 0.1135 | 0.1532 | 89.70 | 10.287 | 0.013 | |
|
|||||||
16 | [ |
1.9650 | 0.2384 | 0.2409 | 67.71 | 32.29 | 0.005 |
[ |
2.5000 | 0.1255 | 0.2235 | 70.10 | 29.83 | 0.07 | |
[ |
2.1667 |
|
0.1961 | 73.13 | 26.85 | 0.02 | |
[ |
2.1667 | −0.1245 | 0.1806 | 74.46 | 25.52 | 0.02 | |
[ |
|
0.1754 |
|
|
|
0.016 | |
SPPC | 1.9903 | 0.1228 | 0.1859 | 87.60 | 12.37 | 0.03 |
The adaptive estimation methods in [
The distributions of QE have been calculated in different multipliers. The sample ratios of QE value (i.e.,
A comparison of performances between the proposed SPPC and previous works is implemented by using their own compensation circuits. Multipliers with different widths are synthesized by Synopsys Design Compiler using a standard cell library of TSMC 0.18
Comparisons of performances with other methods.
Width (bits) | Multiplier | Area ( |
Power (mW) | Delay (ns) | Power-delay product (mW·ns) |
---|---|---|---|---|---|
8 | Ideal | 3392 | 1.030 | 5.82 | 5.995 |
[ |
2396 | 0.667 | 6.14 | 4.095 | |
[ |
|
0.639 | 5.81 | 3.713 | |
[ |
2251 |
|
5.85 | 3.674 | |
[ |
2246 | 0.636 | 5.80 | 3.689 | |
[ |
2307 | 0.682 |
|
3.519 | |
SPPC | 2242 | 0.633 | 5.22 |
|
|
|
|||||
10 | Ideal | 5154 | 1.293 | 6.60 | 8.534 |
[ |
3758 | 0.833 | 6.97 | 5.806 | |
[ |
3479 | 0.789 | 6.26 | 4.940 | |
[ |
3395 | 0.777 | 6.62 | 5.144 | |
[ |
3252 | 0.715 | 6.13 | 4.383 | |
[ |
|
0.842 |
|
4.982 | |
SPPC | 3358 |
|
6.09 |
|
|
|
|||||
12 | Ideal | 7455 | 1.773 | 7.24 | 12.837 |
[ |
5286 | 1.137 | 7.61 | 8.653 | |
[ |
5144 | 1.064 | 6.67 | 7.097 | |
[ |
5161 | 1.099 | 7.43 | 8.166 | |
[ |
4942 |
|
6.60 |
|
|
[ |
|
1.040 |
|
6.822 | |
SPPC | 5056 | 1.012 | 6.63 | 6.710 | |
|
|||||
16 | Ideal | 13554 | 2.562 | 8.06 | 20.650 |
[ |
10058 | 1.563 | 8.41 | 12.145 | |
[ |
9692 | 1.486 | 7.84 | 11.650 | |
[ |
9508 | 1.476 | 8.08 | 11.926 | |
[ |
9390 |
|
7.81 | 10.230 | |
[ |
|
1.403 |
|
10.635 | |
SPPC | 9312 | 1.329 | 7.67 |
|
In general, there exists a trade-off between the hardware overhead and the accuracy in these compensation circuits. The multiplier proposed in [
In order to comprehensively compare the performances of different multipliers, we consider their power-delay products as the standard of comparisons, which are listed in the last column of the Table
The QEC performance of the proposed SPPC is verified by means of a 20 taps low-pass direct form FIR filter. The filter is designed to have 8 MHz pass-band (with a 40 MHz sampling frequency) and 70 dB attenuation in the stop-band for a CR detector. All the widths of input, output, and coefficient of the FIR filter are 16 bits, and the internal adders of the FIR filter are 22 bits. The input for test is a 5 MHz sinusoidal signal with a sampling rate of 40 MHz.
Four different multipliers (
Comparisons of experimental results.
Multiplier | Mean | Variance | Relative error of peak-value (%) |
---|---|---|---|
[ |
|
0.315 |
|
[ |
0.054 | 0.327 | 0.0101 |
[ |
0.069 | 0.417 | 0.0094 |
SPPC | 0.043 |
|
0.0084 |
In CR detectors, it is very important to detect the signal’s spectral peak-values for determining whether the channel is idle [
By further dividing the minor truncated section of Booth multiplier into the adaptive compensation and constant compensation sections, we rebuilt the adaptive QEC for fixed-width multipliers. According to the numbers of 1 in the sequence of nonzero Booth recoding label we propose a new QEC method to generate the compensation carries. The simulation results have shown that the QE of the SPPC is smaller compared with the existing methods. The proposed QEC method and SPPC are useful for the DSP system with a large width multipliers and higher precision requirements.
The authors declare that there is no conflict of interests regarding the publication of this paper.
The authors gratefully acknowledge the support of “Specialized Research Fund for the Doctoral Program of Higher Education” (Grant no. 20120201120026) and “the Fundamental Research Funds for the Central Universities.”