The crosscorrelation method allows phasenoise measurements of highquality devices with very low noise levels, using reference sources with higher noise levels than the device under test. To implement this method, a phasenoise analyzer needs to compute the crossspectral density, that is, the Fourier transform of the crosscorrelation, of two time series over a wide frequency range, from fractions of Hz to tens of MHz. Furthermore, the analyzer requires a high dynamic range to accommodate the phase noise of highquality oscillators that may fall off by more than 100 dB from closein noise to the noise floor at large frequency offsets. This paper describes the efficient implementation of a crossspectrum analyzer in a lowcost FPGA, as part of a modern phasenoise analyzer with very fast measurement time.
Phase noise, the random phase fluctuations of a periodic signal, is an important parameter to characterize highfrequency devices, in particular reference oscillators and microwave synthesizers. Phase noise is important because it has a large impact on the performance of many applications [
There exist various methods for phasenoise measurement, of which the crosscorrelation method achieves the best sensitivity and the widest frequency range, at the expense of a relatively complex setup [
In this paper, we will first review the basics of modelling phase noise and give an outline of the associated terminology. After that, the basics of phasenoise measurement methods will be discussed. Finally, the design and implementation of a novel crossspectrum FFT analyzer in a lowcost FPGA are described in detail.
A perfect fixedfrequency oscillator without noise would produce a perfect sine wave. In reality, any oscillator is affected by internal random noise processes, such as thermal and flicker noise, as well as aging and external influences, such as temperature and vibrations. To be able to characterize the phase noise of a real oscillator, its output signal can be modelled by
Phase fluctuations are characterized in the frequencydomain by their onesided power spectral density
The standard measure of phase noise in the frequencydomain is the singlesideband phasenoise
The simplest phasenoise measurement method is the direct spectrum measurement using a spectrum analyzer. However, this method is only suitable for sources with relatively high noise because the phase noise of the spectrum analyzer must be significantly lower than the noise of the device under test. Furthermore, the dynamic range of this method is very limited because the carrier signal is not suppressed.
Another class of measurement methods are the frequencydiscriminator methods. The advantage of these methods is that they do not require a reference oscillator. However, these methods cannot achieve the sensitivity of the phase detector methods described below [
The method whose implementation is described in Section
The basic principle of the quadrature method is depicted in Figure
Block diagram of the quadrature method. The reference oscillator (REF) is phaselocked to the device under test (DUT). The output of the phase detector (mixer) is first amplified with a low noise amplifier and then measured with a baseband spectrum analyzer.
The main disadvantage and the limiting factor for the measurement accuracy of this method is that the reference source must exhibit significantly lower phase noise than the DUT because any noise on the reference is added to the DUT noise. One possible solution of this problem is to use two identical sources as DUT and reference, so that the two sources contribute the same amount of noise to the output. The measured noise power is then twice the noise power of a single source, assuming the phase noise of the two sources is uncorrelated.
Another disadvantage of the quadrature method is that the PLL forms a highpass filter for the phase noise, as it inherently tries to compensate for phase fluctuations. Therefore, the PLL loop bandwidth must be made substantially lower than the lowest required noise frequency. Depending on the frequency stability of the DUT and reference, the loop bandwidth cannot be made arbitrarily small because the PLL might lose lock [
The crosscorrelation method solves the problem of the reference source noise by using two independent reference sources and phasedetector circuits (see Figure
Block diagram of the crosscorrelation method. This method uses two independent reference sources (REF1, REF2) and phase detectors (mixers). The two baseband outputs are measured with a crossspectrum analyzer.
In a crossspectrum FFT analyzer, the discrete Fourier transforms (DFTs) of the two input signals are computed and the DFTs are multiplied pointwise, taking the complex conjugate of one signal, to obtain an estimate of the crossspectrum. Several of these crossspectra can then be averaged.
The uncorrelated noise products will have random amplitude and phase in the DFT and will therefore be eliminated by the averaging; they will decrease proportionally to
However, for the correlated part of the noise, the product equals the squared magnitude. Therefore, more averages will improve the estimation of the correlated noise, that is, the phase noise of the DUT. Once the uncorrelated noise is averaged away, the variance of the power estimate will decrease proportionally to
In effect, we can accurately measure a noise source that has a lower noise level than the noise floor of a single measurement channel by using the crosscorrelation method. An extensive tutorial of the crosscorrelation method can be found in [
This section describes the implementation of a wideband crossspectrum analyzer for phasenoise measurement in a lowcost Spartan6 FPGA (Field Programmable Gate Array) from Xilinx.
Figure
Architecture of the crossspectrum analyzer and the signal processing inside the FPGA.
Inside the FPGA, the two channels are processed by a cascade of decimators with downsampling factors of 10 and then fed to the signal processing stages to compute the crossspectral density of the two channels. Decimating by a factor of 10 has the advantage that the resulting plot has a constant number of samples per decade. Multiple correlations are summed up in an accumulator memory for averaging in every stage. The accumulated correlations are read out via a softcore microprocessor that provides the output interface. Figure
Architecture of one signal processing stage. One complex FFT block, in combination with a split block, is used to compute the DFTs of the two real input channels.
The logarithmically spaced frequency ranges are important because phasenoise power spectral densities are always plotted in a loglog scale. In the lowfrequency range, the frequency resolution therefore needs to be much smaller than in the highfrequency range. When computing the DFT (Discrete Fourier Transform) of a signal, the frequency resolution is proportional to
Another benefit of this architecture is that the measurement time to obtain one estimate of the power spectral density is dramatically reduced in the highfrequency ranges. If we again assume a frequencyresolution requirement of 1 Hz and want to estimate the spectral density using one FFT, we would require a measurement time of 1 s, because the measurement time is inversely proportional to the frequency resolution. Using the implemented architecture, we can perform multiple FFTs and correlations in the highfrequency stages in parallel, while the lowestfrequency stage may only be able to perform one correlation in the given measurement time.
The cascade of decimators provides antialiasing filtering and downsampling for the FFT stages. The first decimator stage operates at an input sampling rate of 125 MHz and is downsampled to 12.5 MHz. It was implemented as a combination of a cascaded integrator comb (CIC) filter [
The required specification for the decimation filter was alias suppression of at least 60 dB and passband flatness of 0.1 dB. The transition bandwidth should not exceed 50% of the output bandwidth. This means that the usable bandwidth is 75% of the total output bandwidth.
For example, if such a filter was implemented as a single FIR filter, the number of required coefficients would be over a hundred; see Table
Number of required multipliers for optimal FIR filter implementation, depending on the decimationrate allocation.





1  10  119  6 
2  5  72  4 
5  2  31  2 
To reduce the number of required multipliers, it is often beneficial to choose a filter configuration consisting of a CIC filter followed by an FIR filter and distribute the overall downsampling between the two filters [
Theoretically there are four different possibilities to distribute the downsampling rate of 10 between two filters:
Frequency responses of the CIC filter, FIR filter, and combined filter. The CIC filter and FIR filter have downsampling rates of 5 and 2, respectively. The frequency axis is relative to the input sampling rate.
The number of actually used multipliers depends on how well the algorithm that synthesizes the netlist for the FPGA can exploit the hardware oversampling and the coefficient symmetry. Furthermore, it also depends on the bitwidth of the data and coefficients. For this example, the Xilinx tools generated a filter using three multipliers.
Windowing is performed before the FFT to prevent spectral leaking. The implemented window is a 4term minimumsidelobe BlackmanHarris window that has large sidelobe suppression of 92 dB but a relatively large equivalent noise bandwidth (ENBW) of 2 bins [
To increase the number of available FFT samples for averaging, stage 3 to stage 5 employ an overlapping block in front of the windowing. This technique accelerates the convergence of the averaged power spectral densities, which is important to reduce the measurement time at the lower sampling rates.
When the squared magnitude of
If overlapping of 50% is used, the individual FFT samples are correlated. This means that the variance will decrease more slowly. A good approximation of the variance reduction (for more than ten averages) is
The FFT blocks compute the Discrete Fourier Transforms (DFT) of the two windowed input sequences using intellectual property (IP) cores from Xilinx. The length of the DFT at all stages is 1024 samples; the bitwidth of the input and output sequences increases substantially from the first stage to the last stages to accommodate the larger dynamic range in the lowfrequency stages.
The FFT IP cores compute the standard DFT, which takes one complexvalued input sequence to produce one complexvalued output sequence. In this application, however, we need to compute the DFTs of two realvalued input sequences at the same time. The simplest solution to this problem would be to use two independent FFT cores but this would be a waste of FPGA resources.
To save resources, we use the wellknown trick for computing the DFTs of two real sequences using only one complex DFT [
We can exploit this symmetry to compute the DFTs of two real sequences
Using this algorithm, the cost of computing the DFT of two real, length
After the splitting block, the two transformed sequences are multiplied using a complex multiplier block to compute the complexvalued crossspectrum. Before multiplication, the imaginary part of the sequence from channel b is inverted to obtain the complex conjugate. Finally, multiple correlations are summed up in an accumulator memory which can accommodate more than 10,000 correlations. The accumulator memories of all stages can then be read out and the averaged crossspectrum can be displayed to the user.
The crossspectrum analyzer described above was successfully implemented in the commercially available APPH6040 signal source analyzer from Anapico [
Crosscorrelation phasenoise measurement with the APPH6040. The DUT was ultralowphasenoise 100 MHz OCXO. The grey trace shows a measurement with only one correlation. The blue trace shows a measurement with
Crosscorrelation phasenoise measurement of a freerunning wideband VCO at 2.16 GHz with the APPH6040. Single correlation (blue) and maximum correlation (brown) per individual decades. Same measurement time of 1.2 sec for both traces.
We have presented the implementation of a novel crossspectrum FFT analyzer architecture for phasenoise measurements, which was successfully integrated into the commercially available APPH6040 signal source analyzer from Anapico.
Several efficient signal processing techniques had to be employed to enable integration of the FFT analyzer into a lowcost FPGA. For example, the use of CIC filters for signals with high sample rates dramatically reduces the number of required hardware multipliers, a scarce resource in lowcost FPGAs. Furthermore, the successive downsampling architecture uses FFT blocks with small length to cover a large measurement bandwidth, which saves memory inside the FPGA.
The authors declare that there is no conflict of interests regarding the publication of this paper.
Financial support by the Swiss Commission for Technology and Innovation is gratefully acknowledged (CTI projects 11904.2 PFNMNM and 13461.1 PFLENM).