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A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics calibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel samples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work, the offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the timing mismatch is estimated by performing the correlation calculation of the outputs of subchannels and corrected by an improved fractional delay filter based on Farrow structure. Applied to a four-channel 12-bit 400 MHz TIADC, simulation results show that, with calibration, the SNDR raises from 22.5 dB to 71.8 dB and ENOB rises from 3.4 bits to 11.6 bits for a 164.6 MHz sinusoidal input. Compared with traditional methods, the proposed schemes are more feasible to implement and consume less hardware resources.

Modern signal processing applications emerging in the telecommunications and instrumentation industries need high-speed and high-resolution analog-to-digital converters (ADCs). The time-interleaved ADCs (TIADCs) provide an effective way to achieve high sampling rate maintaining high resolution. However, the fabrication errors result in a variety of mismatch errors, constricting the conversion precision of the TIADC. Among them, the main mismatches are offset, gain, and timing mismatches [

In recent years, many research institutes and universities have carried out researches on calibration technology for mismatch errors among channels of TIADC. The calibration of offset and gain mismatches is fairly straightforward, which can be done by adders and multipliers [

In this brief, low complexity calibration algorithms are designed to mitigate the impact of the three main channel mismatches. All calibration algorithms are in digital domain. The calibration method is effective and capable of reducing all three mismatches errors. The rest of this brief is organized as follows: Section

A block diagram and a timing diagram of a TIADC are shown in Figure

The block diagram for an

The offset mismatches are mainly caused by the offsets of operational amplifiers and comparators, which are the results of the mismatches of the devices and the asymmetric circuit structures and the fabrication errors. The gain mismatches are mainly due to the capacitor mismatches in the circuits and the parasitic capacitors of MOS transistors and operational amplifiers. The offset voltage of each sub-ADC can be obtained by a cumulative average calculation of the digital outputs of sub-ADCs, and the differences between them are the offset mismatches of TIADCs, while the gain of each sub-ADC can be obtained by a cumulative average calculation of the absolute values of the digital outputs of sub-ADCs. In this work, the calibration of gain mismatch and offset mismatch is cascaded in a scheme as shown in Figure

Cascaded calibration of offset and gain mismatch scheme based on LMS iteration.

Exponential smoothing filter.

Response of exponential averager with different

The overall framework of the proposed timing mismatch calibration scheme is shown in Figure

Block diagram of the proposed calibration scheme.

Figure

Time domain description of nonuniform sample in a two-channel TIADC.

According to (

Time mismatch calibration technique for a two-channel TIADC.

Assuming that a four-channel TIADC is considered, we choose channel 1 as a reference channel and calibrate the timing mismatches of channels 2, 3, and 4 with respect to channel 1. The error extraction steps are as follows:

The mismatch errors between channel 3 and channel 1 are firstly estimated, and the estimated error is proportional to

When channel 3 is calibrated, it can be considered as a reference channel, and the mismatch errors of channel 2 and channel 4 can be estimated. The estimated errors are proportional to

So the estimation formula of a four-channel TIADC can be written as

Since the parallel alternate sampling time delay of TIADC cannot be precisely controlled, the timing mismatch errors have been a major system error. Commonly, a method that uses a programmable delay line or PLL can realize a precise clock delay adjustment, but this is not enough to meet the ps level clock precision for GHz sampling frequency. In this work, the timing mismatch correction is realized by an all-pass digital filter. Timing mismatch correction uses the delay characteristic of filter to achieve timing mismatch compensation.

Considering only the timing mismatch, the Fourier transform of the output of TIADC is

Finally, the Fourier transform of the output of TIADC is

Formula (

According to the above formula, the filter is divided into many subfilters

Block diagram of a filter based on Farrow structure.

However, the traditional calibration scheme with the Farrow filter as shown in Figure

Hardware comparison of the traditional filter and the improved filter.

Channel | The traditional scheme [ | The proposed scheme | ||||
---|---|---|---|---|---|---|

Channels of TIADC | 2 | 4 | 8 | 2 | 4 | 8 |

Adder units | 30 | 90 | 210 | 30 | 40 | 70 |

Multiplier units | 35 | 105 | 245 | 35 | 45 | 75 |

The traditional calibration scheme with the Farrow filter.

Block diagram of the proposed improved Farrow filter

In order to verify the effectiveness of the calibration algorithms, we implemented them in a 12-bit 4-channel TIADC model in MATLAB platform. The sampling frequency,

The channel mismatches of TIADC.

Channel | Channel 1 | Channel 2 | Channel 3 | Channel 4 |
---|---|---|---|---|

Offset mismatch | 0 | 0.2 | −0.1 | 0.05 |

Actual gain | 1 | 0.95 | 1.03 | 0.96 |

Gain mismatch | 1 | 1.053 | 0.971 | 1.042 |

Timing mismatch | 0 | 2% | 1% | −1.5% |

The mismatch convergence process is shown in Figure

Convergence curves of the proposed calibration method.

Offset mismatch convergence curve

Gain mismatch convergence curve

Timing mismatch convergence curve

Dynamic analysis results with single-frequency input signal.

Before calibration

After calibration

Figure

SNDR versus normalized input frequency (with offset and gain mismatches).

SNDR versus input frequency (with timing mismatch).

Previous analyses are based on a single-frequency input signal, since the nature signal is not of single frequency and is often complicated by a number of different frequency components. Here, we further verify the proposed calibration techniques with a multifrequency input signal. The multifrequency input signal is composed by several noramlized frequencies: 0.064, 0.129, and 0.194. In order to prevent exceeding the ADC conversion range, the input signal magnitude is reduced to 0.9. Figure

Dynamic analysis results with multifrequency input signal.

Before calibration

After calibration

Table

Performance comparison.

[ | [ | [ | This work | |
---|---|---|---|---|

Channels | 4 | 4 | 16 | 4 |

Mismatch types | Timing | Gain, timing | Gain, offset, timing | Gain, offset, timing |

Filter (taps) | 11 | 82 | 31 | |

Adders | 100 | / | 10^{6} | 49 |

Multipliers | 125 | / | 10^{6} | 53 |

Convergence time (samples) | 4 × 10^{4} | 10^{5} | 10^{5} | 1.0 × 10^{4} |

In this paper, we focus on all-digital calibration structures and algorithms to mitigate the impact of mismatches of TIADC; the presented calibration methods have the merits of low hardware resource consumption and fast calibration. Simulation results show that the performance of TIADC is enhanced significantly by using the proposed calibration technique.

The authors declare that they have no competing interests.