Advances in Condensed Matter Physics
Volume 2015 (2015), Article ID 423791, 6 pages
http://dx.doi.org/10.1155/2015/423791

Research Article

Analysis of Low Dimensional Nanoscaled Inversion-Mode InGaAs MOSFETs for Next-Generation Electrical and Photonic Applications

C. H. Yu,¹ X. Y. Chen,1,2 X. D. Luo,¹ W. W. Xu,¹ and P. S. Liu¹

¹Jiangsu Key Laboratory of ASIC Design, Nantong University, Nantong 226019, China
²Laboratory of Advanced Material, Fudan University, Shanghai 200438, China

Received 21 October 2014; Accepted 17 December 2014

Academic Editor: Wen Lei

Copyright © 2015 C. H. Yu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

The electrical characteristics of In0.53Ga0.47As MOSFET grown with Si interface passivation layer (IPL) and high gate oxide HfO₂ layer have been investigated in detail. The influences of Si IPL thickness, gate oxide HfO₂ thickness, the doping depth, and concentration of source and drain layer on output and transfer characteristics of the MOSFET at fixed gate or drain voltages have been individually simulated and analyzed. The determination of the above parameters is suggested based on their effect on maximum drain current, leakage current, saturated voltage, and so forth. It is found that the channel length decreases with the increase of the maximum drain current and leakage current simultaneously. Short channel effects start to appear when the channel length is less than 0.9 μm and experience sudden sharp increases which make device performance degrade and reach their operating limits when the channel length is further lessened down to 0.5 μm. The results demonstrate the usefulness of short channel simulations for designs and optimization of next-generation electrical and photonic devices.

1. Introduction

In0.53Ga0.47As alloys with higher electron mobility are ideal channel materials to implement metal-oxide-semiconductor filed effect transistors (MOSFETs) [1, 2]. In0.53Ga0.47As is believed to be easier to obtain unpinned surface Fermi level and thus can potentially provide better transistor performances compared to other III-V materials. At present, low dimensional nanoscaled III-V semiconductor MOSFETs have received particular attention for their potential applications in photodetectors and solar cells [3–10]. As MOSFET scaling approaches physical and technical limits, various specific gate oxides and passivation techniques have been developed to further increase the device performance of In0.53Ga0.47As MOSFETs. Among them, silicon interface passivation layer (IPL) technique has been successfully employed where silicon IPL acts as a barrier layer to prevent reactions between oxygen and In0.53Ga0.47As layer [11]. The bonds between oxygen and Ga atoms which are closely associated with interface states are replaced by Ga-Si and As-Si bonds during the growth of silicon interface layer [12]. Another functional layer, Ga₂O₃, Al₂O₃, or HfO₂, is also usually deposited as gate oxide in MOSFET structures to improve drain currents [13]. High performance In0.53Ga0.47As MOSFET with silicon IPL and HfO₂ gate oxide has been demonstrated experimentally. However, quantitative analysis of device behavior of this kind of MOSFET is still further needed.

In this paper, the electrical characteristics of nanoscaled In0.53Ga0.47As MOSFET grown with Si IPL and high gate oxide HfO₂ layer are investigated. The effects of various parameters, such as thickness of Si IPL and HfO₂ layers and thickness and doping concentration of drain and source areas, on drain current and are systematically analyzed. Changes of threshold voltage, subthreshold characteristics translation, and saturation region due to short-channel effect caused by decrease of In0.53Ga0.47As channel length are also investigated.

2. Method and Device Structure

Schematic device structure of the In0.53Ga0.47As MOSFET is shown in Figure 1. The thickness of unintentionally doped In0.53Ga0.47As channel layer, silicon IPL, and HfO₂ gate oxide layer is 200 nm, 1 nm, and 10 nm, respectively. All the lengths of gate , source , and drain are equal to 5 μm. The extended length L ext between source and drain contacts is 10 μm. The doping concentration in source and drain areas is . The transverse width of this MOSFET is 600 μm. Physical models applied in our simulation include drift-diffusion equation, band gap narrowing (OldSlotboom), doping-dependent degradation and high field saturation for mobility, Fowler-Nordheim tunneling model for gate leakage current, and Shockley-Read-Hall (SRH) recombination models [14].

Figure 1: Schematic device structure of In0.53Ga0.47As MOSFET.

3. Results and Discussion

Figure 2 shows output and transfer characteristics with a thickness of Si IPL varying from 0.5 nm to 2.5 nm at a fixed gate or drain voltage. Maximum drain current, , increases linearly with the decrease of thickness of Si IPL as shown in the first inset. This increase can be accounted for by the increase of electric field strength under gate electrode with decrease of thickness of Si IPL, which subsequently raises the electron concentration induced in In0.53Ga0.47As channels. The interpretation can also explain the increase of power-up current and leakage current with decrease of thickness of Si IPL in the transfer characteristics curves in the second inset. Simultaneously, the effect of Si IPL as a barrier layer between oxygen and In0.53Ga0.47As layers may be diminished by the decrease of its thickness. The significant increases of when the gate voltages approach larger negative voltages, as the arrow indicates, are attributed to the depletion in the drain area close to gate electrode in In0.53Ga0.47As channels, which increases tunneling probability of carriers between drain and gate electrode [15]. Therefore, the determination of thickness of Si IPL should be a result of compromise between drain currents and role of a barrier layer. A value between 1.0 nm and 1.5 nm is suggested to be set for the thickness of Si IPL based on above simulation results.

(a)

(b)

Figure 2: Si IPL thickness dependence on output (a) and transfer (b) characteristics.

Figure 3 shows output and transfer characteristics with a thickness of gate oxide HfO₂ layer varying from 5 nm to 25 nm at a fixed gate or drain voltage. Due to the variation of electric field strength under gate electrode, maximum drain current and power-up current increase with decrease of thickness of HfO₂ layer. Stronger and are beneficial to improving device performance of In0.53Ga0.47As MOSFETs. Leakage current also exhibits sharp increase with decrease of thickness of HfO₂ layer as explained in Figure 2, especially when the thickness is reduced to 5 nm. This occurrence is not desired to improve device performance. Based on these results, an ideal value of thickness of HfO₂ layer should be kept larger than 10 nm.

Figure 3: Gate oxide HfO₂ thickness dependence on output and transfer characteristics.

Figure 4 shows influences of doping depth of source and drain layer on output and transfer characteristics at a fixed gate or drain voltage. The decrease of doping depth of source and drain layers leads to a decrease of maximum drain current and an increase of turn-on voltage . The former decrease is negative for device development, whereas the latter increase is desired for it is helpful to enlarge the linear operation zone of In0.53Ga0.47As MOSFETs. Different from the aforementioned effects of Si IPL thickness and HfO₂ thickness, the doping depth of source/drain layer has obvious influence on instead of . increases quickly with increase of doping depth. Therefore, a larger doping depth in source and drain layers is preferred for improving device performance. However, increase of doping depth is restricted by the geometrical sizes of In0.53Ga0.47As MOSFETs themselves.

Figure 4: Source/drain layer doping depth dependence on output and transfer characteristics.

Figure 5 shows influences of doping concentration of source and drain layer on output and transfer characteristics at a fixed gate or drain voltage. The increase of doping concentration produces a desired increase of maximum drain current and an undesired decrease of turn-on voltage . As a result for balance between and , a middle-value doping concentration is preferred in practice. When the doping concentration increases ten times from to , only increases about 40%, indicating that impurity scattering which inhibits electrical current increasing begins to dominate [16]. Here, the doping concentration of source/drain layer also has obvious influence on instead of as previous doping depth.

Figure 5: Source/drain layer doping concentration dependence on output and transfer characteristics.

Figure 6 shows influences of channel length on output and transfer characteristics at a fixed gate or drain voltage. Saturated drain current and saturated voltage both increase with the decrease of channel length. The appearance of saturated drain current is a result of unvaried pinch-off voltage at the point where the potential drop across the oxide at the drain terminal is equal to threshold voltage . When the channel length is further lessened down from 0.5 μm to 0.1 μm, the depletion region at the drain terminal extends laterally into the channel, reducing the effective channel length and causing the drain current to be no more saturated. This is the so-called channel length modulation that drain currents begin to move upward with increase of drain voltage when the channel length is substantially shortened as Figure 6(a) illustrates. Meanwhile, the reduction of channel length causes the drain terminate to be closer to source terminate, producing an obvious increase of leakage current and weaker effect of gate electrode on drain currents, as Figure 6(b) shows. Power-up current shows a linear relationship with channel length. This is consistent with previous reports [14].

(a)

(b)

Figure 6: Channel length dependence on output (a) and transfer (b) characteristics.

Figure 7 shows influences of channel length on threshold voltage and subthreshold characteristics at a fixed drain voltage. A transverse shift of subthreshold characteristics is observed for different channel lengths, an important feature of drain induced barrier lowing (DIBL) effect. The DIBL effect is a result of increase of injected electrons from source area to channel induced by lowering of potential barrier height between drain and source electrodes when the channel length is lessened [17]. The shift of subthreshold characteristics starts to become most obvious and the device performance degrades quickly when the channel length is lessened down to a critical value of 0.5 μm, much bigger than that of Si-based npn MOSFETs [18, 19]. In the InGaAs-based MOSFETs, the channel layer InGaAs is unintentionally doped whereas the channel layer in Si-based devices is -type doped, which will induce less Fermi energy difference between drain and source electrodes. Then the corresponding potential barrier height in the InGaAs MOSFETs is comparatively smaller than that of Si-based MOSFETs [20–22]. This is the physical mechanism where DIBL effect is much obvious in the InGaAs MOSFETs. Threshold voltage experiences a similar sudden decrease when the channel length is lessened down to the same value of 0.5 μm. These results mean that the InGaAs MOSFETs start to show short channel effect at a value of 0.9 μm of channel length and reach their operating limits when the channel length is further lessened down to 0.5 μm.

Figure 7: Channel length dependence on threshold voltage and shift of subthreshold characteristics.

4. Conclusion

In conclusion, the electrical characteristics of In0.53Ga0.47As MOSFET grown with Si IPL and high gate oxide HfO₂ layer have been investigated in detail. The decrease of Si IPL thickness and gate oxide HfO₂ thickness is beneficial to improving device performance by increasing the maximum drain current. However, rather small Si IPL thickness and gate oxide HfO₂ thickness result in sharp increase of leakage current and device performance degradation. The increase of source and drain layer doping depth brings about larger maximum drain current and almost has little negative influence on saturated voltage and leakage current. Unfortunately, increase of doping depth is limited by the geometrical size of MOSFETs themselves. The increase of source and drain layer doping concentration also has dual influences. On the one hand, it helps to improve the maximum drain current. On the other hand, it produces a lowered saturated voltage and smaller device linear operating limits. The decrease of channel length increases the maximum drain current and leakage current simultaneously. Short channel effects start to appear when the channel length is lessened down to about 0.9 μm and experience sudden sharp increases which make device performance degrade and reach their operating limits when the channel length is further lessened down to 0.5 μm.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgments

This work was supported in part by the National Natural Science Foundation of China (Grant nos. 11104150, 11274330, and 61474067), the Key Natural Science Foundation of the Jiangsu Higher Education Institutions of China (Grant no. 14KJA510005), and the National Basic Research Program of China (Grant no. 2011CBA00700).

References

F. Zhu, H. Zhao, I. Ok et al., “A high performance In0.53Ga0.47 As metal-oxide-semiconductor field effect transistor with silicon interface passivation layer,” Applied Physics Letters, vol. 94, no. 1, Article ID 013511, 2009.

Y. Xuan, P. D. Ye, and T. Shen, “Substrate engineering for high-performance surface-channel III-V metal-oxide-semiconductor field-effect transistors,” Applied Physics Letters, vol. 91, no. 23, Article ID 232107, 2007.

H. Xia, Z.-Y. Lu, T.-X. Li et al., “Distinct photocurrent response of individual GaAs nanowires induced by n-type doping,” ACS Nano, vol. 6, no. 7, pp. 6005–6013, 2012.

J. Miao, W. Hu, N. Guo et al., “Single InAs nanowire room-temperature near-infrared photodetectors,” ACS Nano, vol. 8, no. 4, pp. 3628–3635, 2014.

J. Miao, W. Hu, and N. Guo, “High-responsivity graphene/InAs nanowire heterojunction near-infrared photodetectors with distinct photocurrent on/off ratios,” Small, 2014.

Z. Liu, T. Luo, B. Liang et al., “High-detectivity InAs nanowire photodetectors with spectral response from ultraviolet to near-infrared,” Nano Research, vol. 6, no. 11, pp. 775–783, 2013.

N. Guo, W. Hu, L. Liao et al., “Anomalous and highly efficient InAs nanowire phototransistors based on majority carrier transport at room temperature,” Advanced Materials, vol. 26, no. 48, pp. 8203–8209, 2014.

H. Zeng, G. Duan, Y. Li, S. Yang, X. Xu, and W. Cai, “Blue luminescence of ZnO nanoparticles based on non-equilibrium processes: defect origins and emission controls,” Advanced Functional Materials, vol. 20, no. 4, pp. 561–572, 2010.

H. Zeng, C. Zhi, Z. Zhang et al., “‘White graphenes’: boron nitride nanoribbons via boron nitride nanotube unwrapping,” Nano Letters, vol. 10, no. 12, pp. 5049–5055, 2010.

Z. Liu, J. Xu, D. Chen, and G. Shen, “Flexible electronics based on inorganic nanowires,” Chemical Society Reviews, vol. 44, no. 1, pp. 161–192, 2015.

N. Taoka, M. Harada, Y. Yamashita, T. Yamamoto, N. Sugiyama, and S.-I. Takagi, “Effects of Si passivation on Ge metal-insulator-semiconductor interface properties and inversion-layer hole mobility,” Applied Physics Letters, vol. 92, no. 11, Article ID 113511, 2008.

J. Ivanco, T. Kubota, and H. Kobayashi, “Deoxidation of gallium arsenide surface via silicon overlayer: a study on the evolution of the interface state density,” Journal of Applied Physics, vol. 97, no. 7, Article ID 073712, 2005.

Y. Xuan, Y. Q. Wu, H. C. Lin, T. Shen, and P. D. Ye, “Submicrometer inversion-type enhancement-mode InGaAs MOSFET with atomic-layer-deposited Al₂O₃ as gate dielectric,” IEEE Electron Device Letters, vol. 28, no. 11, pp. 935–938, 2007.

C.-H. Yu, Q.-Z. Luo, X.-D. Luo, and P.-S. Liu, “Donor-like surface traps on two-dimensional electron gas and current collapse of AlGaN/GaN HEMTs,” The Scientific World Journal, vol. 2013, Article ID 931980, 6 pages, 2013.

Y.-K. Choi, D. Ha, T.-J. King, and J. Bokor, “Investigation of gate-induced drain leakage (GIDL) current in thin body devices: single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs,” Japanese Journal of Applied Physics, vol. 42, no. 4, pp. 2073–2076, 2003.

W. Hu, X. Chen, X. Zhou, Z. Quan, and L. Wei, “Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: a 2d simulation study,” Microelectronics Journal, vol. 37, no. 7, pp. 613–619, 2006.

M. Si, J. J. Gu, X. Wang et al., “Effects of forming gas anneal on ultrathin InGaAs nanowire metal-oxide-semiconductor field-effect transistors,” Applied Physics Letters, vol. 102, no. 9, Article ID 093505, 2013.

A. D. Franklin, M. Luisier, S.-J. Han et al., “Sub-10 nm carbon nanotube transistor,” Nano Letters, vol. 12, no. 2, pp. 758–762, 2012.

S. H. Park, Y. Liu, N. Kharche et al., “Performance comparisons of III-V and strained-Si in planar FETs and nonplanar FinFETs at ultrashort gate length (12 nm),” IEEE Transactions on Electron Devices, vol. 59, no. 8, pp. 2107–2114, 2012.

T. Yamada, Y. Nakajima, T. Hanajiri, and T. Sugano, “Suppression of drain-induced barrier lowering in silicon-on-insulator MOSFETs through source/drain engineering for low-operating-power system-on-chip applications,” IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 260–267, 2013.

F. Xue, A. Jiang, H. Zhao et al., “Sub-50-nm MOSFETs with various barrier layer materials,” IEEE Electron Device Letters, vol. 33, no. 1, pp. 32–34, 2012.

S. Tewari, A. Biswas, and A. Mallik, “Impact of different barrier layers and indium content of the channel on the analog performance of InGaAs MOSFETs,” IEEE Transactions on Electron Devices, vol. 60, no. 5, pp. 1584–1589, 2013.