Advances in Condensed Matter Physics
Volume 2018 (2018), Article ID 2426863, 7 pages
https://doi.org/10.1155/2018/2426863

Research Article

DC Performance Variations of SOI FinFETs with Different Silicide Thickness

Jun-Sik Yoon

POSTECH Information Research Laboratories, Pohang 37673, Republic of Korea

Correspondence should be addressed to Jun-Sik Yoon; junsikyoon@postech.ac.kr

Received 30 January 2018; Revised 4 April 2018; Accepted 12 April 2018; Published 17 May 2018

Academic Editor: Da-Ren Hang

Copyright © 2018 Jun-Sik Yoon. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

DC performance and the variability of -type silicon-on-insulator dopant-segregated FinFETs with different silicide thickness () are analyzed. DC parameters including threshold voltage, low-field-mobility-related coefficient, and parasitic resistance are extracted from -function method for the comparison of DC performance and variability, and the correlation analysis. All the devices show similar subthreshold characteristics, but the devices with thicker have greater threshold voltages. The devices with thicker suffer from the DC performance degradation and its greater variations because the Schottky barrier height at the NiSi/Si interface increases and fluctuates greatly. This effect is validated by greater threshold voltages, larger parasitic resistances, and high correlations among all the DC parameters for the thicker . The devices with thicker also have higher low-frequency noise because of larger parasitic resistances and their correlated mobility degradations. Therefore, the device with relatively thin is expected to have better DC performance and variability concerns.

1. Introduction

Silicon-on-insulator (SOI) MOSFETs maintain short channel immunity successfully due to the absence of substrate leakage current [1]. SOI-based devices having fin-shaped [2], ultra-thin-body [3], or gate-all-around [4] channel regions attain great scalability without short channel degradation. Meanwhile, dopant-segregated SOI MOSFETs have been considered as one of the promising candidates due to their several advantages over the planar bulk MOSFETs: low Schottky barrier height (SBH) at the silicide/semiconductor interface, possibility of low-temperature process, and near-abrupt junction formation [5–9]. Not only MOSFETs but also tunneling FETs also utilize abrupt doping profile to enhance the band-to-band tunneling transport at the source/channel junction [10, 11].

Two-step annealing process during silicidation was suggested to decrease the lateral excursion of silicide into the channel region [12]. The influence of NiPt thickness prior to silicidation on the DC performance of SOI MOSFETs has been studied [13]. Increasing the NiPt thickness increased the contact resistance due to the decreased interfacial area between silicide and semiconductor but decreased the variations of sheet resistance due to its full silicidation. In this regard, it is necessary to analyze both DC performance and its variability in the perspective of the silicidation for the nanoscale dopant-segregated SOI MOSFETs.

Thus, DC performance and variations of SOI FinFETs with different silicide thickness () were investigated. Then, the variability sources inducing the drain current () variations were studied using the correlation analysis. Low-frequency noise was also measured for the detailed analysis of the devices with different .

2. Materials and Methods

(100) undoped SOI with 140-nm-thick buried oxide (BOX) and 20-nm-thick top Si region was prepared. BOX overetching process was performed to define omega-shaped fin structure as shown in Figure 1(b) of [13]. After the formation of gate stack (HfO₂, TiN, amorphous-Si), Arsenic dopants were implanted at extension regions to reduce the underlap resistance. After defining nitride spacer regions with the spacer length () of 20 nm, low-energy implantation and annealing at 1070°C and 1.5 s were done for the source/drain (S/D) regions. Different from [13] where the NiPt with different thickness of 5 or 10 nm was deposited, the same 10-nm-thick NiPt (4% Pt) was deposited and annealed under two-step rapid thermal process (RTP) conditions to remove the unreacted NiPt in the middle. Instead, different RTP temperature and time conditions were used to form the NiSi with different of 8 and 10 nm. Otherwise, all the measured devices have the equivalent number of fins () of 2, fin width () of 40 nm, fin height () of 20 nm, extension length () of 80 nm, and gate length () of 40 nm. The detailed process flow and device geometry are shown in [13].

All the devices have the active regions with equivalent size and structure, so the differences of DC performances and the variations are induced mostly by different . Figure 1 shows the possible variability sources of the S/D regions. Uneven NiSi/Si interface [14] and random dopant fluctuation (RDF) [15, 16] can also fluctuate the contact resistivity and thus induce the DC performance variations. Different NiSi/Si contact area by different would also affect the DC performance and variations because typical transfer lengths, defined as the distances that carriers below the contact travel before entering into the contact, of SOI devices are in the order of 100 nm [17, 18], which is longer than . Different RTP conditions involved with different can vary the device performance by statistical piping effect [19] or lateral encroachment of NiSi into the S/D extension regions [20]. To understand DC performance and its variations for different , their transfer characteristics were measured using Keithley 4200 semiconductor characterization system, whereas low-frequency noise was measured using HP 89410A vector signal analyzer.

Figure 1: 3D schematic diagram of the SOI FinFETs. Geometrical parameters such as gate length (), spacer length (), extension length (), and silicide thickness () are also specified. Top left figure describes the real device structure, and red-colored phrases indicate the possible variability sources.

3. Results and Discussion

3.1. DC Performance and Variations at Different Silicide Thickness

and transconductance () of the 50 measured devices each with different of 8 and 10 nm are shown in Figure 2. Each wafer has a different , and the measured devices with each are at the same position of each wafer to minimize the die-to-die variations between two different . Gate voltage () is swept from 0.0 to 1.3 V in steps of 0.02 V, and drain voltages () are 0.05 and 1.0 V. Red lines indicate the averages of and for each . In both linear and saturation regimes, the devices with of 8 nm have greater DC performance by showing higher on-state currents (), while the subthreshold characteristics for of 8 and 10 nm are similar. Figure 2(c) shows that all the devices with of 8 and 10 nm do not have ambipolar effects at high of 1.0 V near the off-state, validating the absence of Schottky contact [13].

(a)

(b)

(c)

Figure 2: DC performance and variations of the SOI FinFETs with the of (a) 8 and (b) 10 nm at drain voltage () of 0.05 V and (c) 1.0 V. The number of measured devices is 50 for each .

values of the 20 measured devices each with different and are shown in Figure S1. are extracted at the gate overdrive voltage () of 1.0 V, where is the threshold voltage () extracted from constant current method (CCM) at  A (). The devices with of 8 nm have smaller for all . But the difference of between two different is smaller for greater because the ratio of the NiSi/Si contact area between two different decreases. Additionally, raised S/D structure would be beneficial to improve the DC performance by increasing the NiSi/Si contact area. But for raised S/D structure, likewise, thicker also decreases the contact area, increases the contact resistance, and thus degrades the DC performance [21].

Several parameters from the transfer characteristics are extracted to analyze the DC performance variations: , low-field-mobility-related coefficient (), and parasitic resistance (). values are extracted using CCM or -function method [16, 22]. is measured at  A, whereas from -function method () is extracted from the -axis intercept of the linearly extrapolated curve as shown in Figure 3.

Figure 3: -function variations of the SOI FinFETs with of 8 and 10 nm. Almost all the -functions satisfy the linearity condition in the strong inversion regime.

The simple and general expression of at low in the strong inversion regime is given by

where is defined as ( is effective mobility and is oxide capacitance). -function is simply expressed as

According to (2), -function is linear in the strong inversion regime if or does not depend on . In other words, the -function does not satisfy the linearity condition if the devices suffer from surface roughness scattering greatly [22]. Another assumption is that is almost invariant to and smaller than in the strong inversion regime, which is satisfied in this study. Almost all the measured devices also meet the linearity condition at of 0.05 V (Figure 3) because all the devices have omega-shaped structure with ultra-thin fin channel, which induces volume inversion and thus attenuates the surface roughness scattering.

Figure 4 shows , , and of the measured devices at of 0.01, 0.02, 0.03, 0.04, and 0.05 V extracted from -function method. Average and are independent of , whereas increases slightly as increases. includes the band-bending by gate voltage as well as the body-effect expressed by , where is the body-effect coefficient ( is simply approximated as 1 for fully depleted devices), thus showing a slight increase of with the slope of as increases [23]. The devices with of 8 nm show greater and smaller due to greater NiSi/Si contact area.

Figure 4: Average and standard deviations of dc parameters for the SOI FinFETs with of 8 nm (black) and 10 nm (red) at different : , , and .

The devices with of 10 nm have greater variations of , , and (Figure 4). Standard deviations () of and for of 10 nm increase by 62.4 and 48.5%, respectively, with respect to those for of 8 nm. Not only but also variations are severer for of 10 nm ( mV) than for of 8 nm ( mV) at all different .

3.2. DC Performance Variability Analysis

To investigate why the devices with of 10 nm suffer from smaller DC performance and greater variations, correlation analysis of with off-state currents (), , , and is done in Figure 5. Spearman’s correlation is used to calculate the correlation coefficient (ρ) [15]. values are at of 0.0 V, whereas all the values are extracted at the gate overdrive voltage () of 0.8 V () to neglect the effect [24]. Since all the devices have similar SS and no gate-induced drain leakages, is mostly determined by   ( and −0.907 for of 8 and 10 nm, resp.). Due to these perspectives, therefore, a slight correlation between and along with is expected.

Figure 5: Scatter plots of at () of 0.8 V with respect to the DC parameters (, , , and ) for the SOI FinFETs at of 0.05 V. All the linear regressions indicate the sensitivity of with respect to the DC parameters.

Nonetheless, there are correlations between , , and for of 10 nm (left of Figure 5). In addition, for of 10 nm is correlated with and , whereas for of 8 nm is independent of and at all different . is also correlated with for of 10 nm (), whereas the correlation is small for of 8 nm ().

These high correlations among all the DC parameters (, , , ) and for of 10 nm are related to the high SBH at the NiSi/Si interface. Higher SBH for thicker is expected due to greater lateral encroachment of NiSi into the S/D extension regions [19, 25]. Greater (or ) and larger for of 10 nm are the indicatives of higher SBH according to equation (2) in [26] and higher contact resistivity [27], respectively. Higher SBH for thicker requires much band-bending for the carrier injection from source (related with and ) and impedes carrier flow under operation (related with , , and thus ) [28]. For the low-SBH devices, the SBH variations induce the on-state performance variations, not the variations [26]. Therefore, the variations for of 8 nm are dominantly induced by other variability sources (gate work function (WF) variation [24], RDF [15], and interface traps [29]) except the SBH. And that is why for of 8 nm is not correlated with , , and .

Greater variations of all the DC parameters for of 10 nm can also explain the increased SBH and its variations. The variations for SOI FinFETs are dominantly affected by NiSi/Si contact resistance [20, 27]. The NiSi/Si interface consists of NiSi crystal grains having different WF and surface roughness [14]. The extension regions suffer from RDF [15] along with the WF variations, having different SBH at each of NiSi crystal grains and also for each of the devices. And this induces the SBH variations greatly for of 10 nm due to smaller contact area.

Figure 6 shows the relative contributions to the variations with respect to the DC parameters each. When the DC parameters are correlated with each other, the contributions to the variations of for the correlated portion are calculated using the correlation coefficient, sensitivity (the slope of scatter plots in Figure 5), and standard deviations [24]. All the correlated portions are presented as the shaded area. All the three DC parameters are correlated with each other and the variations affect the variations greatly for of 10 nm, whereas they are independent and the variations affect the variations greatly for of 8 nm.

Figure 6: variations and variations of the dc parameters (, , and ) contributing to the variations for of 8 and 10 nm.

3.3. Low-Frequency Noise Analysis

Low-frequency noise was measured at of 0.05 V and at the overdrive voltage () of 0.3 V (Figure 7). Frequency range was from 1 to 1000 Hz, and the 10 devices each with of 8 and 10 nm, closest to the average , were measured. All the results follow the 1/ trend except at the frequency near 1 Hz where Lorentzian-type noise plateau is observed due to the small-area devices. The devices with of 10 nm have greater average for all the frequency range.

(a)

(b)

Figure 7: Drain current noise spectral density () measured at of 0.05 V and the overdrive voltage () of 0.3 V for of (a) 8 and (b) 10 nm. The number of measured devices, close to the average , is 10 each.

Figure 8 shows normalized by of the devices with different at from 0.1 to 0.6 V in steps of 0.1 V measured at 10 Hz. In case of from 0.3 to 0.6 V, the normalized values are almost independent of , where the noise induced by () is dominant to the device [30]. The noise within the channel () is from the Si/SiO₂ interface and the channel itself, whereas is from the S/D contact at NiSi/Si interface. But the quality of Si/SiO₂ interface is almost similar for all the devices because the only difference is RTP, performed under low temperature around 300~450°C [13, 19, 20, 31, 32] enough not to induce the Si/SiO₂ interface damage. In spite of that, the devices with of 10 nm have greater because high SBH close to the lightly doped extension region decreases (related to ) which is correlated with . Greater for of 10 nm is also explained by the lateral encroachment of NiSi into the S/D extension regions. More lateral encroachment of NiSi for thicker induces higher SBH, which impedes the carrier flow and decreases the channel length [33]. These physical phenomena increase according to equation (3) of [30]; thus the greater for of 10 nm is obtained (Figure 8). As a result, the devices with of 10 nm have greater normalized for all .

Figure 8: Normalized at 10 Hz with respect to at different .

4. Conclusions

DC performance and variability of the dopant-segregated SOI FinFETs with different are analyzed in terms of the DC parameters extracted from -function method and Spearman correlation, respectively. Thicker degrades DC performance by decreasing and and fluctuates , , , and greatly because the SBH increases greatly and varies along with WF variation and RDF at the S/D region. In addition, the devices with of 10 nm suffer from large low-frequency noise due to high SBH, which is caused by greater lateral encroachment of NiSi into the S/D extension regions and related to greater variations and correlations of , , , and . Therefore, the device with relatively thin is promising to improve DC performance and minimize the variation.

This variability study would be helpful to design nanoscale devices having a few dopants and small contact area because the SBH values and variations of the devices depend on greatly.

Data Availability

All the data analyzed in this study are included in this published article.

Conflicts of Interest

The author declares that there are no conflicts of interest regarding the publication of this paper.

Acknowledgments

The author would like to thank SEMATECH for device fabrication. This work was supported in part by the Ministry of Science and ICT, South Korea, through the ICT Consilience Creative Program under Grant IITP-2017-R0346-16-1007 supervised by the Institute for Information and Communications Technology Promotion.

Supplementary Materials

Supplementary materials contain one figure (Figure S1). Figure S1: on-state resistance () as a function of fin width () for different of 8 and 10 nm. The number of fins () for each device is 20. As increases from 40 to 80 nm, the difference of between two different decreases from 36 to 23%. (Supplementary Materials)

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