DC Performance Variations of SOI FinFETs with Different Silicide Thickness

DC performance and the variability of n-type silicon-on-insulator dopant-segregated FinFETs with different silicide thickness ( T sili ) are analyzed. DC parameters including threshold voltage, low-field-mobility-related coefficient, and parasitic resistance are extracted from Y -function method for the comparison of DC performance and variability, and the correlation analysis. All the devices show similar subthreshold characteristics, but the devices with thicker T sili have greater threshold voltages. The devices with thicker T sili suffer from the DC performance degradation and its greater variations because the Schottky barrier height at the NiSi/Si interface increases and fluctuates greatly. This effect is validated by greater threshold voltages, larger parasitic resistances, and high correlations among all the DC parameters for the thicker T sili . The devices with thicker T sili also has higher low-frequency noise because of larger parasitic resistances and their correlated mobility degradations. Therefore, the device with relatively-thin T sili is expected to have better DC performance and variability concerns.


Introduction
Silicon-on-insulator (SOI) MOSFETs maintain short channel immunity successfully due to the absence of substrate leakage current [1]. SOI-based devices having fin-shaped [2], ultra-thinbody [3], or gate-all-around [4] channel regions attain great scalability without short channel degradation. Meanwhile, dopant-segregated SOI MOSFETs have been considered as one of the promising candidates due to their several advantages over www.videleaf.com the planar bulk MOSFETs: low Schottky barrier height (SBH) at the silicide/semiconductor interface, possibility of lowtemperature process, and near-abrupt junction formation [5][6][7][8][9]. Not only does MOSFETs, but also tunneling FETs also utilize abrupt doping profile to enhance the band-to-band tunneling transport at the source/channel junction [10,11]. Two-step anneal process during silicidation was suggested to decrease the lateral excursion of silicide into the channel region [12]. The influence of NiPt thickness prior to silicidation on the DC performance of SOI MOSFETs has been studied [13]. Increasing the NiPt thickness increased the contact resistance due to the decreased interfacial area between silicide and semiconductor, but decreased the variations of sheet resistance due to its full silicidation. In this regard, it is necessary to analyze both DC performance and its variability in the perspective of the silicidation for the nanoscale dopantsegregated SOI MOSFETs.
Thus, DC performance and variations of SOI FinFETs with different silicide thickness (T sili ) were investigated. Then, the variability sources inducing the drain current (I ds ) variations were studied using the correlation analysis. Low-frequency noise was also measured for the detailed analysis of the devices with different T sili .

Materials and Methods
(100) undoped SOI with 140-nm-thick buried oxide (BOX) and 20-nm-thick top Si region was prepared. BOX over-etching process was performed to define omega-shaped fin structure as shown in Figure 1b of [13]. After the formation of gate stack (HfO 2 , TiN, amorphous-Si), Arsenic dopants were implanted at extension regions to reduce the underlap resistance. After defining nitride spacer regions with the spacer length (L sp ) of 20 nm, low-energy implantation and annealing at 1070 °C and 1.5 s was done for the source/drain (S/D) regions. Different from [13] where the NiPt with different thickness of 5 or 10 nm was deposited, the same 10-nm-thick NiPt (4 % Pt) was deposited and annealed under two-step rapid thermal process (RTP) www.videleaf.com conditions to remove the unreacted NiPt in the middle. Instead, different RTP temperature and time conditions were used to form the NiSi with different T sili of 8 and 10 nm. Otherwise, all the measured devices have the equivalent number of fins (N fin ) of 2, fin width (W fin ) of 40 nm, fin height (H fin ) of 20 nm, extension length (L ext ) of 80 nm, and gate length (L g ) of 40 nm. The detailed process flow and device geometry are shown in [13]. Geometrical parameters such as gate length (L g ), spacer length (L sp ), extension length (L ext ), silicide thickness (T sili ) are also specified. Top left figure describes the real device structure, and red-colored phrases indicate the possible variability sources.
All the devices have the active regions with equivalent size and structure, so the differences of DC performances and the variations are induced mostly by different T sili . Figure 1 shows the possible variability sources of the S/D regions. Uneven NiSi/Si interface [14] and random dopant fluctuation (RDF) [15,16] can also fluctuate the contact resistivity and thus induce the DC performance variations. Different NiSi/Si contact area by different T sili would also affect the DC performance and variations because typical transfer lengths, defined as the distances that carriers below the contact travel before entering into the contact, of SOI devices are in the order of 100 nm [17,18], which is longer than the L ext . Different RTP conditions involved with different T sili can vary the device performance by statistical piping effect [19] or lateral encroachment of NiSi into the S/D extension regions [20]. To understand DC performance and its variations for different T sili , their transfer characteristics were measured using Keithley 4200 semiconductor characterization system, whereas low-frequency noise was measured using HP 89410A vector signal analyzer. www.videleaf.com  Figure 2c shows that all the devices with the T sili of 8 and 10 nm do not have ambipolar effects at high V ds of 1.0 V near the off-state, validating the absence of Schottky contact [13].

DC Performance and Variations at Different Silicide Thickness
R on (= V ds /I on ) values of the 20 measured devices each with different W fin and T sili are shown in Figure S1. The I on are extracted at the gate overdrive voltage ). The devices with the T sili of 8 nm have smaller R on for all the W fin . But the difference of R on between two different T sili is smaller for greater W fin because the ratio of the NiSi/Si contact area between two different T sili decreases. Additionally, raised S/D structure would be beneficial to improve the DC performance by increasing the NiSi/Si contact area. But for raised S/D structure, likewise, thicker T sili also decreases the contact area, increases the contact resistance, and thus degrades the DC performance [21]. www.videleaf.com Several parameters from the transfer characteristics are extracted to analyze the DC performance variations: V th , low-fieldmobility-related coefficient (X 0 ), and parasitic resistance (R sd ).
V th values are extracted using CCM or Y-function method [16,22]. V th_CCM is measured at I th = W eff /L g ·10 -8 A, whereas V th from Y-function method (V th_y ) is extracted from the x-axis intercept of the linearly-extrapolated curve as shown in Figure 3.
The simple and general expression of the I ds at low V ds in the strong inversion regime is given by (1) where X 0 is defined as μ eff ·C ox ·W eff /L g (μ eff is effective mobility and C ox is oxide capacitance). Y-function is simply expressed as the devices suffer from surface roughness scattering greatly [22].
Other assumption is that I ds ·R sd is almost invariant to V gs and smaller than V ds in the strong inversion regime, which is satisfied in this study. Almost all the measured devices also meet the linearity condition at the V ds of 0.05 V (Figure 3) because all the devices have omega-shaped structure with ultra-thin fin channel, which induces volume inversion and thus attenuates the surface roughness scattering.  Figure 4 shows the V th_y , X 0 , and R sd of the measured devices at the V ds of 0.01, 0.02, 0.03, 0.04, and 0.05 V extracted from Yfunction method. Average X 0 and R sd are independent of V ds , whereas V th_y increases slightly as V ds increases. V th_y includes the band-bending by gate voltage as well as the body-effect expressed by m/2·V ds , where m is the body-effect coefficient (m is simply approximated as 1 for fully-depleted devices), thus showing a slight increase of V th_y with the slope of V ds /2 as V ds increases [23]. The devices with the T sili of 8 nm show greater X 0 and smaller R sd due to greater NiSi/Si contact area. The devices with the T sili of 10 nm have greater variations of V th_y , X 0 , and R sd (Figure 4). Standard deviations (σ) of X 0 and R sd for the T sili of 10 nm increase by 62.4 and 48.5 %, respectively, with respect to those for the T sili of 8 nm. Not only V th_y but also V th_CCM variations are severer for the T sili of 10 nm (σ = 45 mV) than for the T sili of 8 nm (σ = 22 mV) at all different V ds . To investigate why the devices with the T sili of 10 nm suffer from smaller DC performance and greater variations, correlation analysis of I on with off-state currents (I off ), V th_y , X 0 , and R sd is done in Figure 5. Spearman's correlation is used to calculate the correlation coefficient (ρ) [15]. I off values are the I ds at the V gs of 0.0 V, whereas all the I on values are extracted at the gate overdrive voltage (V gs -V th_y ) of 0.8 V (I on_y ) to neglect the V th_y effect [24]. Since all the devices have similar SS and no gateinduced drain leakages, I off is mostly determined by V th_y (ρ = -0.781 and -0.907 for the T sili of 8 and 10 nm, respectively). Due to these perspectives, therefore, a slight correlation between I on_y and I off along with V th_y is expected.

DC Performance Variability Analysis
Nonetheless, there are correlations between I off , V th_y , and I on_y for the T sili of 10 nm (left of Figure 5). In addition, V th_y for the T sili of 10 nm is correlated with X 0 (ρ = -0.530) and R sd (ρ = 0.491), whereas V th_y for the T sili of 8 nm is independent of X 0 (ρ = -0.077) and R sd (ρ = 0.200) at all different V ds . X 0 is also correlated with R sd for the T sili of 10 These high correlations among all the DC parameters (I off , V th_y , X 0 , R sd ) and I on_y for the T sili of 10 nm are related to the high SBH at the NiSi/Si interface. Higher SBH for thicker T sili is expected due to greater lateral encroachment of NiSi into the S/D extension regions [19,25]. Greater V th_CCM (or V th_y ) and larger R sd for the T sili of 10 nm are the indicatives of higher SBH according to the equation 2 in [26] and higher contact resistivity [27], respectively. Higher SBH for thicker T sili requires much band-bending for the carrier injection from source (related with I off and V th_y ) as well as impedes carrier flow under operation (related with X 0 , R sd , and thus I on_y ) [28]. For the low-SBH devices, the SBH variations induce the on-state performance variations, not the V th variations [26]. Therefore, the V th variations for the T sili of 8 nm are dominantly induced by other variability sources (gate work function (WF) variation [24], RDF [15], interface traps [29]) except the SBH. And that is why the V th_y for the T sili of 8 nm is not correlated with X 0 , R sd , and I on_y .
Greater variations of all the DC parameters for the T sili of 10 nm can also explain the increased SBH and its variations. The R sd variations for SOI FinFETs are dominantly affected by NiSi/Si contact resistance [20,27]. The NiSi/Si interface consists of NiSi crystal grains having different WF and surface roughness [14]. The extension regions suffer from RDF [15] along with the WF variations, having different SBH at each of NiSi crystal grains and also for each of the devices. And this induces the SBH variations greatly for the T sili of 10 nm due to smaller contact area. www.videleaf.com  Figure 6 shows the relative contributions to the I on_y variations with respect to the DC parameters each. When the DC parameters are correlated each other, the contributions to the variations of I on_y for the correlated portion are calculated using the correlation coefficient, sensitivity (the slope of scatter plots in Figure 5), and standard deviations [24]. All the correlated portions are presented as the shaded area. All the three DC parameters are correlated each other and the X 0 variations affect the I on_y variations greatly for the T sili of 10 nm, whereas they are independent and the R sd variations affect the I on_y variations greatly for the T sili of 8 nm. measured. All the results follow the 1/f trend except at the frequency near 1 Hz where Lorentzian-type noise plateau is observed due to the small-area devices. The devices with the T sili of 10 nm have greater average S Ids for all the frequency range.  Figure 8 shows the S Ids normalized by I ds 2 of the devices with different T sili at the V ov from 0.1 to 0.6 V in steps of 0.1 V measured at 10 Hz. In case of the V ov from 0.3 to 0.6 V, the normalized S Ids values are almost independent of V ov , where the noise induced by R sd (S Rsd ) is dominant to the device [30]. The noise within the channel (S Rch ) is from the Si/SiO 2 interface and the channel itself, whereas S Rsd is from the S/D contact at NiSi/Si interface. But the quality of Si/SiO 2 interface is almost similar for all the devices because the only difference is RTP, performed under low temperature around 300~450 °C [13,19,20,31,32] enough not to induce the Si/SiO 2 interface damage. In spite of that, the devices with the T sili of 10 nm have greater S Rch because high SBH close to the lightly-doped extension region decreases the X 0 (related to μ eff ) which is correlated with the R sd . Greater S Rch for the T sili of 10 nm is also explained by the lateral encroachment of NiSi into the S/D extension regions. More lateral encroachment of NiSi for thicker T sili induces higher SBH, which impedes the carrier flow and decreases the channel length  [33]. These physical phenomena increase the S Rch according to the equation 3 of [30], thus the greater S Rch for the T sili of 10 nm is obtained (Figure 8). As a result, the devices with the T sili of 10 nm have greater normalized S Ids for all the V ov .

Conclusions
DC performance and variability of the dopant-segregated SOI FinFETs with different T sili are analyzed in terms of the DC parameters extracted from Y-function method and Spearman correlation, respectively. Thicker T sili degrades DC performance by decreasing I on and g m,max and fluctuates V th , X 0 , R sd , and I on greatly because the SBH increases greatly and varies along with WF variation and RDF at the S/D region. In addition, the devices with the T sili of 10 nm suffer from large low-frequency noise due to high SBH, which is caused by greater lateral encroachment of NiSi into the S/D extension regions and related to greater variations and correlations of V th_y , X 0 , R sd , and I on_y . Therefore, the device with relatively-thin T sili is promising to improve DC performance and minimize the variation.
This variability study would be helpful to design nanoscale devices having a few dopants and small contact area because the SBH values and variations of the devices depend on the T sili greatly.