Analysis of Conduction and Charging Mechanisms in Atomic Layer Deposited Multilayered HfO 2 / Al 2 O 3 Stacks for Use in Charge Trapping Flash Memories

Method for characterization of electrical and trapping properties of multilayered high permittivity stacks for use in charge trapping flash memories is proposed. Application of the method to the case of multilayered HfO2/Al2O3 stacks is presented. By applying our previously developed comprehensive model forMOS structures containing high-κ dielectrics on the J−V characteristics measured in the voltage range without marked degradation and charge trapping (from −3V to +3V), several parameters of the structure connected to the interfacial layer and the conduction mechanisms have been extracted. We found that the above analysis gives precise information on the main characteristics and the quality of the injection layer. C − V characteristics of stressed (with write and erase pulses) structures recorded in a limited range of voltages between−1 V and+1V (where neither significant charge trapping nor visible degradation of the structures is expected to occur) were used in order to provide measures of the effect of stresses with no influence of the measurement process. Both trapped charge and the distribution of interface states have been determined using modified Terman method for fresh structures and for structures stressed with write and erase cycles. The proposed method allows determination of charge trapping and interface state with high resolution, promising a precise characterization of multilayered high permittivity stacks for use in charge trapping flash memories.


Introduction
High permittivity (high-) dielectric stacks are subject of particular interest as material for charge trapping flash memories [1][2][3].Stacks of different high- oxides, such as Al 2 O 3 -TiO 2 -Al 2 O 3 [4], combinations with semiconductor layers such as Al 2 O 3 -Cu 2 O [5], and compound high- oxides [6] have proven to provide effective solutions for the choice of material for trapping layer.
Multilayered high- stacks present increasing interest for researchers [7].Precise characterization of the trapping properties is required in order to describe correctly the functioning of the charge trapping memory devices.
The issues of relation between conduction mechanisms and electrically active defects have been studied [8], as well as the charging mechanisms that are to be considered in the case of charge trapping memories [9,10].The particular role of the blocking layer and effect of double-layered blocking oxide have been studied in [11].
In [12] it has been demonstrated that while inserting thin Al 2 O 3 layer in HfO 2 films, memories exhibit larger memory window, faster program/erase speed, and better  In the present work our aim is to propose a method of characterization of trapping using sensitive nondestructive methods.For this purpose, a structure without blocking layer is used.Oxide and interface charge are characterized by using recently proposed modified Terman method [13].

Fabrication of the Samples and Experimental Procedure
The samples studied here were fabricated on p-type (1 0 0) 7 Ω cm Si substrates.After chemical cleaning, a multilayered stack 5 × (HfO 2 /Al 2 O 3 ) has been deposited by atomic layer deposition.The thickness of each HfO 2 layer is 2.8 nm and that of each Al 2 O 3 layer is 1.0 nm.Calculations of the thicknesses were done based on the previously made calibration of the fabrication process.Total high- stacked layer thickness is therefore 5 × (2.8 + 1.0) nm = 19 nm.After deposition, the samples were subject to rapid thermal annealing in N 2 at 800 ∘ C for 1 min.In order to obtain as thinnest as possible tunneling SiO 2 layer, no particular oxidation was made prior high- stacked layer deposition.As is known, due to thermodynamic instability, an interfacial layer is inevitably grown between the Si substrate and the high- layer [14].Thus, an interfacial oxide layer about 2.5 nm thick has been grown during the fabrication of the structures.This value of the interfacial layer thickness was estimated by previous calibrations of the fabrication process and is in accordance with extrapolations from literature values reported in the work [15].
The gate areas of the devices used in this study were  = 2.5 × 10 −3 cm 2 .Al metal gates were obtained by thermal evaporation and structured by photolithography.Backside of Si substrate was also Al metalized, providing a back ohmic contact.
C-V characteristics were measured in serial mode at the signal level of 24 mV and frequency of 100 Hz with the use of a HP 4284 A LCR-meter. −  (leakage) characteristics were measured by using a HP4140A picoammeter/DC voltage source, for both positive and negative gate polarity, in the voltage range from −6 V to +24 V. Current was measured in  steps of 0.05 V, with a hold time of 5 s, in order to suppress the displacement currents.
A schematic representation of the test Al-high-/SiO 2 -Si structure is shown in Figure 1.

𝐶 − 𝑉 Characteristics of Fresh Structures
First,  −  characteristics of the fresh structure in a limited voltage range between −1 V and +1 V (Figure 2) have been analyzed.Neither significant charge trapping nor visible degradation of the test Al-high-/SiO 2 -Si structures is expected to occur under these measurement conditions, as it was found in our previous works on similar structures.The method described in detail in [13] was used.
Capacitance ( 0 ) of the whole dielectric stack (multilayered HfO 2 /Al 2 O 3 trapping layer/SiO 2 ) was determined using the extrapolation method proposed by Kar et al. [16].Illustration of the application of this method in determination of  0 is given in Figure 2. Value of 1/ 0 is obtained from the intercept of the fitted straight line of the plot of √(d/d g )(1/ 2 ) versus 1/ (Figure 3).
Thus obtained capacitance is  0 = 1152 pF.Corresponding equivalent thickness is 7.49 nm.The flatband voltage obtained

Complete 𝐽-𝑉 Characteristic
Next, - characteristics of the structure for both positive and negative gate polarity until destructive breakdown were studied.Curves for positive and for negative gate were recorded separately on different fresh devices.Typical curves are shown in Figure 4.For negative gate, destructive breakdown is observed at voltages of about 5.65 V, while for positive gate breakdown voltage is much higher, attaining the value of 23.1 V.The situation with the breakdown current values is opposite: for negative bias it is 0.1 fA/m 2 while for positive gate bias it is only 0.02 fA/m 2 .In both cases the breakdown power ( ⋅  g ) is practically the same (0.5 W/m 2 ).This finding indicates that the final destructive breakdown of the structure is dominantly dissipation related.
In order to avoid severe degradation and breakdown, injection current level is to be selected at much lower values than the lowest breakdown current value, that is, 0.02 fA/m 2 .Here, we choose the value of 0.002 fA/m 2 , an order of magnitude lower than the lowest breakdown current measured.Corresponding write voltage (positive) is +10 V, while the corresponding erase voltage (negative) is −4 V.

Low Voltage Segments of 𝐽−𝑉 Characteristic
Several parameters of the interfacial layer and conduction mechanisms can be extracted, by consideration of the  −  characteristics in the narrow voltage range where no marked degradation and charge trapping (from −3 V to +3 V) occur and applying the comprehensive model for structures containing Ta 2 O 5 developed in [17] and explained in detail [18] for structures with various high- dielectrics.The method is briefly described below.
Band diagram of the considered structure constructed on the same way as it was described in [17] for Al-Ta 2 O 5 /SiO 2 -Si structures is shown in Figure 5. Data for nanolaminated Al 2 O 3 /HfO 2 films are taken from the work [19].
First, the voltage drop across the whole dielectric stack (referred to as oxide voltage,  ox ) corresponding to the applied voltage on the structure ( g ) is calculated by using the expression: where  fb is the flatband voltage and  s the voltage drop in silicon (surface potential).Depending on the oxide voltage level, injection current in SiO 2 is due to direct tunneling through a trapezoidal barrier or due to Fowler-Nordheim tunneling trough a triangular barrier.Direct tunneling current density ( t ) through the injecting SiO 2 layer is given by the following expression: and for Fowler-Nordheim tunneling it is given by where  is the electron charge, ℎ is Planck's constant,  * is the effective tunneling mass of carriers in SiO 2 ,  in is the  thickness of injecting SiO 2 layer, Φ is the tunneling barrier height, and  in is the electric filed in the injecting SiO 2 layer.Different carriers from the silicon substrate produce this current: electrons in the case of gate positively biased and holes in the case of gate negatively biased [17].Total current through the injection layer ( in ) is where  hc is the hoping conductivity of the injecting SiO 2 layer.
The current density due to the Poole-Frenkel effect in the high- stacked trapping layer ( PF ) is given by the following expression: where  hk is the effective electric field in the high- stacked trapping layer,  PF is temperature-dependent defect-related constant having dimensions of conductivity,  is the Boltzmann constant,  0 is the dielectric constant of vacuum, and  T =  2 is the optical frequency dielectric constant ( is the effective refractive index of the high- stacked trapping layer).Theoretical oxide voltage is calculated as where  hk is the thickness of the high- stacked trapping layer.Theoretical determination of the parameters is done numerically using the steady state condition for the current densities In Figure 6 the experimental results (circles) for leakage currents as a function of the oxide voltage that are compared with the theoretically obtained curves are shown.Very good agreement between the theoretical and experimental curves is obtained, confirming that expected conduction mechanisms are the most important ones in the studied structure.Saturation of the current in inversion (at positive gate polarity), observed for oxide voltages higher than 1.5 V, is explained to be due to the exhaustion of minority carriers (electrons in p-type substrate) [17].This part has a shape of a reverse biased diode characteristics and can be included in a complete model for the device using an equivalent circuit containing a diode connected in series with the structure [18].Since the main aim of this work is to study conduction and trapping properties of a nanolaminated high- dielectric, we do not consider this part of the characteristics.Details on the fitting method and determination of the parameters are explained in [17].
Applicability of the theory used in this work has been previously tested on many various metal-high-/SiO 2 -Si structures, which is resumed in our review paper [18].In inversion (positive gate in the case of a p-type substrate) saturation occurs at approximately 2 V.In accumulation, the straightforward application of the theory is limited by the appearance of wear-out and charge trapping at higher voltages, depending on the interfacial layer thickness and the high- composition and quality.Usually, limiting values are between 3 V and 7 V.In this work only small effect of charge trapping (slightly lower leakage current) is manifested for the three rightmost measured points, thus justifying the use of the theory in the given measurement range.
Optimal values of the parameters used in computation are displayed in Table 1.Nonlinear successive adjustment of the parameters ( in ,  hc ,  PF , Φ e , and Φ h ) fitting method has been used, as it was described in the work [17].Barrier heights for injections of electrons (Φ e ) and holes (Φ h ) from the Si substrate play important role in the considered range along with the conduction mechanism in the high- layer.For dielectric films substantially thicker than 10 nm, voltage regions with dominant conduction mechanism for similar structures can be clearly separated, as is shown in [20].
However, as we have demonstrated in [21], in the case of nanosized high- dielectrics methods based on the use of single dominant conduction mechanism are inconsistent and the use of models that involve simultaneously several mechanisms has to be considered.Significant information on the quality of both the injection and the high- stacked trapping layer is obtained using the extracted parameters given in Table 1.First, the precise value of the injection layer thickness (electrical thickness) is obtained ( in = 2.53 nm).This is the most relevant figure describing the electrical properties of the injection layer.Second, the values of barrier heights for electrons and holes are 3.15 eV and 4.7 eV, respectively, as is expected for stoichiometric SiO 2 layer.In addition, the value of the hopping conductivity of this layer ( hc = 1 × 10 −16 Ω −1 cm −1 ) is exceptionally low, showing that the injecting layer is of particularly good quality, since the hopping conductivity currents are substantially lower than the injection currents which are the main mechanism allowing proper functioning of the charge trapping flash memories.For a comparison, the value of the hopping conductivity obtained for Al/ZrO 2 /Al 2 O 3 /ZrO 2 /SiO 2 /Si structures ( hc = 3.5 × 10 −11 Ω −1 cm −1 ) [9] is markedly higher than for the structures studied here.Such low value as obtained here is close to the value obtained for Al/Ta 2 O 5 /SiO 2 /Si structures ( hc = 5 × 10 −17 Ω −1 cm −1 ) where dielectric (Ta 2 O 5 ) is obtained by thermal oxidation of Ta [17], thus providing exceptionally low density of defects.
Therefore, we conclude that the above analysis gives precise information on the main characteristics and the quality of the injection layer.have been tested in order to determine the optimal write voltage providing satisfactory value for the memory window.Such hysteresis loops between the voltages −5 V to +3 V, −5 V to +5 V, and −5 V to +10 V are shown in Figure 7.

𝐶 − 𝑉 Hysteresis
It is important to note the observation that capacitance in accumulation at −5 V has substantially higher value (1300 pF) than that obtained on fresh structures using limited voltage range from −1 V to +1 V (1152 pF).Above difference is not due to the method of extrapolation, which has been shown to give precise estimates of the capacitance of the insulating layer itself, but to some real changes in the dielectric.Namely, as we have shown in the work [22], voltage stress causes an increase of the capacitance in accumulation ( 0 ) by effective thinning of the SiO 2 layer by creation of conductive paths in this layer during the stress, as it was previously found from stress induced leakage current characteristics in the work [23].Detailed study of the variations of  −  characteristics with consecutive runs has been reported in [24].
Hysteresis width Δ fb = 2.1 V is obtained for sweeping between −5 V and +10 V, Δ fb = 2.0 V is obtained for sweeping between −5 V and +5 V, and Δ fb = 1.2 V is obtained for sweeping between −5 V and +3 V. Above values are consistent with the literature results obtained for Al 2 O 3 /HfO 2 stacks on In 0.53 Ga 0.47 As [25].Namely, in [25] it is observed that there is a maximum value of Δ fb between the two Al 2 O 3 /HfO 2 thicknesses ratios of 2.5 nm/3.0 nm and 0.5 nm/2.5 nm higher than or equal to 0.4 V. From our experiment a higher value of 1.2 V is obtained for the thicknesses ratio 1.0 nm/2.5 nm.This value is substantially higher than the value reported for pure HfO 2 [26] under similar conditions.Therefore, it can be concluded that the insertion of Al 2 O 3 between HfO 2 layers for the given thickness ratio substantially increases the trapping in the high- stacked layer.
Values of flatband voltages for runs left from different starting positive voltages and for the runs back right from −5 V are given in Table 2. Corresponding calculated oxide charges are also shown.
As is seen from Figure 6, increase of the turn-around voltage from +5 V to +10 V does not significantly enlarge the hysteresis width (only about 0.1 V).This finding can be explained by rather small increase of the injection current in that voltage region (see Figure 4).Therefore, it is no use to increase the write voltage over 5 V, since the gain in Δ fb is rather small, while the degradation of the structure will become rather important, thus limiting the endurance of the devices.
An important feature of the structures is the observed higher absolute value of the oxide charge after both runs left and runs rights compared to the fresh sample.Therefore, when applying voltages substantially higher than ±1 V, irreversible change of the oxide charge occurs.After this initial irreversible change, repeatable patterns of the − curves are obtained depending generally on the starting voltage.This is a common behavior of the metal/high-/SiO 2 /Si structures, as we have shown in [24].

Detailed Analysis of 𝐶 − 𝑉 Characteristics of Stressed Structures
In this section, - characteristics (measured in a limited voltage range between −1 V and +1 V) of stressed (with write and erase pulses) structures (Figure 8) have been analyzed.Since neither significant charge trapping nor visible degradation of the structures is expected to occur under these measurement conditions, by this method of analysis precise measures of the effect of stresses can be found with no influence of the measurement process itself.It is seen that the write pulse (+5 V for 60 s) causes a shift to the right (trapping of electrons).Erase pulse (−5 V for 60 s) shifts the curve back to the left, as a result of removal of electrons trapped during the write pulse.Holes injected from the substrates at negative gate bias are expected to be responsible for this effect.
Flatband voltages ( fb ) corresponding to the shown curves and the calculated values of the oxide charges ( ox ) are summarized in Table 3.
Oxide charge obtained after the erase pulse (−5 V for 60 s) is practically equal to these obtained from the measured  −  curves with starting point −5 V. Therefore, it is to be concluded that no significant discharging occurs between the end of the erase pulse and the consecutive  −  measurement between −1 V and +1 V.In contrast with this behavior, the absolute value of the oxide charge extracted from  −  measurement after the write pulse (+5 V for 60 s) is substantially lower than this obtained from the measured  −  curves with starting point +5 V. Above finding can be attributed to the discharge of a significant part of negative charge (4.4 × 10 12 cm −2 ) trapped during the write pulse.Most probably, this is the part of the charge that is accumulated at the interface between the injecting SiO 2 layer and the multilayered HfO 2 /Al 2 O 3 stack [9].By adding a blocking layer, the total oxide charge to be retained is expected.However, due to the leakage, retention time for the accumulated charge at the interface of the high- with the injecting layer [27] is expected to be substantially lower than that for the trapped charge.Further improvement of the fabrication process is to be intended towards increasing the part of the charge trapped in the stack.Here described method can be effectively used in such an analysis.In order to analyze in more detail the trapping/detrapping process, detailed analysis of  −  characteristic of fresh and stressed structures using the method described in [13] has been performed here.Results for fresh samples are shown in several steps, while for the others the final figures only are presented.
In Figure 9  in the silicon bandgap obtained on fresh samples is shown.
Reference zero-energy level is set to the top of the valence band ( v ) of Si.Both positions of  v and  c (bottom of the conduction band) are labelled in Figure 9. Exponential tails towards band edges in our work [13] have been attributed to the effect of quantum charge in silicon substrate close to the interface with the dielectric.Using the method described in [13], quantum charge has been determined from the slopes of the curve for the stretch-out of the measured  −  characteristic relative to the ideal one (Δ g ) versus oxide voltage ( ox ).After extraction of the contribution of quantum charge, distribution of interface states displayed in Figure 10  characteristic obtained by the standard method, is shown.In addition, an ideal  −  characteristic corrected for quantum charge is presented.The corrected ideal curve is obtained by subtracting the voltage drop on the quantum charge layer from the measured gate voltage.
In Figure 12 distributions of densities of interface states ( it ) determined by modified Terman method versus energy () in silicon bandgap obtained on fresh and stressed samples during the write cycle are shown.It is seen that the distributions remain practically unchanged.Moreover, no visible changes are observed for further three write/erase cycles.

Conclusions
Proposed method for characterization of multilayered HfO 2 / Al 2 O 3 stacks for use in charge trapping flash memories in this work allows precise characterization of the electrical properties of the structures and the trapping properties.
In the particular case of multilayered HfO 2 /Al 2 O 3 stacks studied in this work, it is found that the used ratio of thicknesses of the homogeneous layers (HfO 2 )/(Al 2 O 3 ) = 2.8 nm/1.0 nm provides excellent conditions for charge trapping and accumulation in the stack.
Based on a refined analysis, it is found that dominant part of the oxide charge is related to the accumulated charge, compared to the trapped charge.In order to improve further the charging properties of the stack, fabrication method for increasing the part due to the charge trapping is to be developed.
Under considered working conditions, no significant generation of interface states is observed.Therefore, no marked variations of the characteristics of the devices with the repeated write/erase cycling are expected.Long-term degradation is to be studied further, using the same methods as used in this work.

Figure 1 :
Figure 1: Schematic representation of the test structure used in this study.

Figure 2 :
Figure 2:  −  characteristic of a fresh structure.

Figure 3 :Figure 4 :
Figure 3: Illustration of the method of determination of the capacitance in accumulation.

Figure 5 :
Figure 5: Energy band diagram for the structure studied in this work.

Figure 6 :
Figure 6: Experimental − characteristics (circles) and theoretical curves (solid lines); full circles are for positive gate bias and empty circles for negative one.
Usually, the structures to be used in trapping memories are characterized by  −  hysteresis.Different sweeping ranges

Figure 8 :
Figure 8:  −  characteristics of the structures after write (+5 V for 60 s, thick line) and erase (−5 V for 60 s, thin line) cycles.For comparison  −  characteristic of the fresh sample (Figure 1) is shown as dotted line.

2 )Figure 9 : 2 )Figure 10 :
Figure 9: Distribution of densities of interface states ( it ) obtained by standard Terman method versus energy () through the silicon bandgap obtained on fresh samples.

Table 1 :
Parameters used in the theoretical calculations shown in Figure6; indices h and e are for holes and electrons, respectively.

Table 2 :
Flatband voltages of the samples for various runs.

Table 3 :
Flatband voltages and oxide charge after the write and the erase pulse.