High step-up dc-dc converter is an essential part in several renewable energy systems. In this paper, a new topology of step-up dc-dc converter based on interleaved structure is proposed. The proposed converter uses three energy storing capacitors to achieve a high voltage gain. Besides the high voltage gain feature, the proposed converter also reduces the voltage stress across the semiconductor switches. This helps in using low rating switching devices which can reduce the overall size and cost of the converter. The operating principle of the proposed converter is discussed in detail and its principle waveforms are analyzed. An experiment is carried out on a 20 V input, 130 V output, and 21 W power prototype of the proposed converter in the laboratory to verify the performance of the proposed converter. An efficiency of 91.3% is achieved at the rated load.
1. Introduction
Several applications require high step-up dc-dc voltage conversion. One of the most common applications is the photovoltaic energy sources where the low input voltage should be stepped-up to high dc-link voltage. Other applications include fuel cell, hybrid electric vehicle (HEV), high-intensity discharge lamp ballasts, and uninterruptible power supplies. A high step-up dc-dc converter is essential for such kind of applications. For such type of high step-up dc-dc voltage conversion, a traditional boost converter shown in Figure 1 will operate at very high duty cycle (above 80%) as the voltage gain of a simple boost converter is 1/1-D. Such high duty cycle will cause severe reverse recovery problem of the output diode. Also the switches in the simple boost converter will experience a high voltage stress as their voltage stress is equal to the output voltage. Moreover, it needs large filter elements to minimize the ripples as it has only one inductor with no ripple cancellation. For this purpose, various high step-up topologies have been reported in the literature [1–3].
Circuit diagram of traditional boost converter.
Two-stage/quadratic boost converter comprising two boost converters can be used to achieve high voltage gain as the voltage gain is equal to the product of the gains of two boost converters, that is, 1/1-D2. However, using two boost converters may degrade the overall efficiency as the overall efficiency is also equal to the product of the efficiencies of two boost converters [4–6]. Inductorless switched capacitor circuits can give high step-up voltage conversion ratio, but they use a large number of switches and gate drives. The efficiency of switched capacitor circuit also is poor [7, 8]. Interleaved or parallel structure is well known for reducing the ripples due to its well-known feature of ripple cancellation among the phases. Moreover, it can handle more power, but it does not help in increasing the step-up voltage gain or reducing the voltage stress on switches [9].
Tapping among the inductors and coupling of various inductors can achieve high step-up voltage conversion ratio by adjusting the turn ratio. However, it is very difficult to perfectly couple inductors and the existence of leakage inductance can create problems of large voltage overshoots [10–14]. Boost converter employing voltage multiplier and three-state switching cells can achieve high voltage gain and also reduces ripple in input current. But the voltage gain of one multiplier cell is not much high and for a very high step-up voltage conversion more numbers of multipliers cells will be needed [15, 16]. Isolated converters such as half-bridge, full-bridge, and flyback can achieve high step-up voltage conversion by adjusting the turn ratio of the transformer. But they have their own problems related to transformers and are more expensive as compared to nonisolated types [17].
To achieve high voltage gain and lower switch stress, a new topology of dc-dc converter is presented in this paper. The circuit diagram is shown in Figure 2. The proposed converter is a three-phase interleaved boost converter with an intermediate capacitor and two output capacitors which forms the floating output. The proposed converter can achieve a very high voltage gain as well as reduce the voltage stress of switches.
Circuit diagram of the proposed converter.
2. Operating Principle of the Proposed Converter
Figure 2 shows the circuit diagram of the proposed converter. It consists of three phases with L1 being the filtering inductor of phase #1, L2 being the inductor of phase #2, and L3 being the filtering inductor of phase #3. Transistors S1, S2, and S3 are the main switches of phase #1, phase #2, and phase #3, respectively. Similarly, D1, D2, and D3 are the rectifying diodes of three phases. VS is the supply voltage, VO is the output voltage, and RL is load resistor. For the analysis of the proposed converter the following assumptions are made:
L1=L2=L3=L (where L is the inductance/phase),
C1=C2=C (where C is the filter capacitor),
all capacitors and inductors are very large, so that their ripples are very small,
the converter always operates in continuous conduction mode (CCM).
The operation of the converter is done at a fixed switching frequency FS and it has a fixed switching period of TS. The operation is such that switches S1, S2, and S3 are turned on and off by two PWM signals which is 180-degree phase shifted. One PWM signal is applied to the gate of S2 and another PWM signal which is 180-degree phase shifted from the first one is applied to the gates of S1 and S3. There is no phase shift between phase #1 and phase #3 and both these phases are at 180-degree phase shift with phase #2. The converter is analyzed for a duty cycle D greater than 50%. There are total four switching states in one switching period. Figure 3 shows the circuit diagram of the proposed converter formed in each state and Figure 4 shows steady state waveforms for the proposed converter.
Operating circuits of the proposed converter. (a) State-I and state-III, (b) state-II, and (c) state-IV.
Steady state waveforms of the proposed converter.
State-I (tO≤t≤t1). State-I starts at t=tO when all the transistors S1–S3 are turned on. During this state all the diodes D1–D3 remain off. Figure 3(a) shows the circuit topology of the proposed converter formed in this state. Inductors L1, L2, and L3 get charged by the supply voltage VS and the currents I1, I2, and I3 through them increase with slopes of VS/L. Capacitor Cin is disconnected from the supply as well as from the load; it neither charges nor discharges and its voltage VCin is constant. Both the output capacitors C1 and C2 discharge to the load and their voltages VC1 and VC2 fall with slopes of -VO/(RLC).
State-II (t1≤t≤t2). State-II begins when switches S1 and S3 are turned off at t=t1. The switch S2 is still on. Diodes D1 and D3 start conducting, whereas diode D2 is still off. Figure 3(b) shows the circuit topology formed in this state. Inductor L2 is still in charging mode and its current I2 rises with a slope of VS/L. Inductors L1 and L3 are in discharge modes and their currents I1 and I3 fall with slopes of (VS-VCin)/L and (VS-VC2)/L, respectively. Capacitor C1 is still in discharge mode and its voltage VC1 is still decreasing with same slope of -VO/(RLC). Capacitors Cin and C2 are charged up by the supply and their voltages VCin and VC2 rises with slopes of I1/Cin and I3/C-VO/(RLC). This state ends at t=t2.
State-III (t2≤t≤t3). This state is similar to state-I. Again all the transistors are on and all the diodes are off. The circuit diagram is the same as in state-I (Figure 3(a)).
State-IV (t3≤t≤t4). This state begins when switch S2 is turned off at t=t3. Switches S1 and S3 are still off. Diode D2 starts conducting and diodes D1 and D3 remain off. Figure 3(c) shows the circuit topology formed in this state. Inductors L1 and L3 are charged by the supply and their currents I1 and I3 rise with slopes of VS/L. Inductor L2 discharges and its current I2 decreases with a slope of (VS+VCin-VC1)/L. Capacitor Cin discharges to load and its voltage VCin falls with a slope of -I2/Cin. Capacitor C1 gets charged and its voltage VC1 rises with a slope of I2/C-VO/(RLC). Capacitor C2 also discharges to load and its voltage falls with a slope of -VO/(RLC). This state ends at t=t4.
3. Steady State Analysis of the Proposed Converter
To simplify the analysis of the proposed converter, the time of each state is expressed in terms of duty cycle D and switching period TS as(1)tO=0sec,t1=DTS-TS2sec,t2=TS2sec,t3=DTSsec,t4=TSsec.
3.1. DC Conversion Ratio
For the voltage conversion ratio M of the proposed converter we will apply the principle of inductor volt second balance (VSB) on inductors L1, L2, and L3. By VSB of inductor L1 we get(2)VSt1-tO+VS-VCint2-t1+VSt3-t2+VSt4-t3=0.The solution of (2) gives(3)VCin=VS1-D.By VSB of inductor L2 we get(4)VSt1-tO+VSt2-t1+VSt3-t2+VS+VCin-VC1t4-t3=0.The solution of (4) gives(5)VC1=VS1-D+VCin.From (3) and (5) we get(6)VC1=2VS1-D. By VSB of inductor L3 we get(7)VSt1-tO+VS-VC2t2-t1+VSt3-t2+VSt4-t3=0.The solution of (7) gives(8)VC2=VS1-D. The output capacitors C1 and C2 remain in series with the supply voltage VS and therefore the output voltage VO of the proposed converter is given by(9)VO=VC1+VC2-VS.By (6), (8), and (7) we get(10)VO=2+D1-DVS.And the voltage conversion ratio M is(11)M=VOVS=2+D1-D.
3.2. Voltage Stress of Semiconductor Devices
Switches S1 and S3 are off in state-II and remain on in the rest of switching period. Referring to Figure 3(b), the off-state voltage (voltage stress) of switches S1 and S2 can be obtained as(12)VS1=VCin=VS1-D,VS2=VC1-VCin=VS1-D.Switch S2 is off only in state-IV. Referring to Figure 3(c) the voltage stress VS3 of switch S3 is given by(13)VS3=VC2=VS1-D.In similar way the maximum voltage drop (voltage stress) of the diodes D1, D2, and D3 can be found out and is given by(14)VD1=-VC1=-2VS1-D,VD2=-VC2+VCin=-VS1-D,VD3=VC2=VS1-D.
3.3. Ripple Current and Ripple Voltage
Referring to Figure 4, the peak to peak ripple Δi1 in the current I1, peak to peak ripple Δi2 in current I2, and peak to peak ripple Δi3 in current I3 are expressed as(15)Δi1=Δi2=Δi3=DVSLFS.Similarly, the peak to peak ripple ΔVCin in voltage VCin can be expressed as(16)ΔVCin=VORLCinFS.The peak to peak ripple ΔVC1 in voltage VC1 and ΔVC2 in voltage VC2 are given by(17)ΔVC1=ΔVC2=DVORLCFS.The peak to peak ripple ΔVO in the output voltage VO is given by(18)ΔVO=2D-1VORLCFS.
4. Experimental Results
To verify the effectiveness of the proposed converter, the parameters listed in Table 1 are used to obtain the theoretical and experimental results of the proposed converter.
Paramaters used for experiment.
Name of parameter
Symbol
Value
Output power
PO
21 [W]
Input voltage
VS
20 [V]
Output voltage
VO
130 [V]
Load resistance
RL
800 [Ω]
Frequency
FS
100 [kHz]
Filter inductor/phase
L
200 [µH]
Intermediate capacitor
Cin
1 [µF]
Output smoothing capacitor
C
1 [µF]
Using (3), (6), (8), and (11) and using the parameters of Table 1, the following results are obtained:(19)D=0.6,VCin=50V,VC1=100V,VC2=50V.
Similarly using the parameters of Table 1 in (12), (13), and (14) gives the voltage stress of semiconductor devices:(20)VS1=50V,VS2=50V,VS3=50V,VD1=-100V,VD2=-50V,VD3=-50V.
To verify the results and performance of the proposed converter an experiment has been carried out in the laboratory on a 21-watt prototype of the proposed converter using the parameters listed in Table 1. A photograph of the hardware of proposed converter is shown in Figure 5.
Photograph of prototype of the proposed converter.
Figure 6 shows the experimental waveforms of the proposed converter for a duty cycle of 60%. The gate signals VG1 and VG2 are shown in Figure 6(a). It can be seen that these two signals are at 180-degree phase shift with each other both have 60% duty cycle. Figure 6(b) shows the waveforms of input and output voltages of the proposed converter. As clear from Figure 6(b) the supply voltage VS to the proposed converter is 20 volts and the output voltage VO is 121.5 volts which is close to the ideal value of 130 volts. Thus the proposed converter is able to produce 130 volts output from 20 volts input at 60% duty cycle and easily achieves a step-up voltage conversion ratio of 6.5. Figure 6(c) shows the waveforms of the voltages across the capacitors C1, C2, and Cin. The voltage VC1 across capacitor C1 is 93 volts and the voltage across each capacitor C2 and Cin is 47 volts which are also close to ideal/theoretically calculated values. The waveforms of the voltage stresses VS1, VS2, and VS3 across the MOSFETs S1, S2, and S3 are shown in Figure 6(d). It can be seen that all the three voltages are equal to 50 volts. Thus the voltage stress across the MOSFETs is almost 2.6 times lower than the output voltage. Figure 6(e) shows the waveforms of the voltage stress across the diodes D1, D2, and D3. As clear from Figure 6(e), the voltage stress VD1 across diode D1 is −98 volts, the voltage stress VD2 across diode D2 is −46 volts, and the voltage stress VD3 across diode D3 is −48 volts. Thus the voltage stress across the diodes is also reduced considerably.
Experimental waveforms of the proposed converter. (a) Waveforms of PWM signals VG1 and VG2 with 60% duty cycle. (b) Waveforms of supply voltage VS and output voltage VO. (c) Waveforms of voltages VC1, VC2, and VCin across capacitors C1, C2 & Cin. (d) Waveforms of voltage stresses VS1, VS2 and VS3 of MOSFETs S1,S2,andS3. (e) Waveforms of voltage stresses VD1, VD2, and VD3 of diodes D1, D2, and D3.
Traditional interleaved boost converters whether of two phases or three phases have step-up voltage conversion ratio of 1/(1-D) and the voltage stress across their switches (transistors and diodes) is equal to the output voltage [18, 19]. Thus, for producing an output voltage of 130 volts from an input voltage of 20 volts, the traditional interleaved boost converter must operate at a duty cycle of 84.6% which is very high as compared to the proposed interleaved boost converter. Also for 130-volt output voltage, the voltage stress across the transistors and diodes of traditional interleaved boost converter will be 130 volts which is also very high as compared to the switch stresses of the proposed converter.
From experimental results, it is clear that the proposed converter has very good performance as compared to the traditional interleaved boost converter. It nearly produces 130-volt output voltage from an input voltage of 16 volts with a duty cycle of 60% whereas the conventional interleaved boost converter will produce the same output at a duty cycle of 84.6% which is very high and can result in severe reverse recovery problems. Thus the proposed converter has considerably higher step-up voltage conversion ratio as compared to traditional interleaved boost converter and it easily overcomes the extreme high duty cycle operation and reverse recovery problem of the output diodes which appear in traditional interleaved boost converter. The voltage stress on the semiconductor devices of the proposed converter is also reduced considerably. Except the voltage stress of diode D1 which is 100 volts, the voltage stress of all other switches in the proposed converter is 50 volts; thus low rating devices can be used which results in reducing the overall cost and size of the converter whereas the voltage stress of the switches of traditional interleaved boost converter is equal to the output voltage, that is, 130 volts. Thus the voltage stress across the switches of the proposed converter is 2.6 times lower than that across the switches of traditional interleaved boost converter.
Figure 7 shows a plot of experimentally measured efficiency of the proposed converter against the load. The load resistor is varied to change the power and efficiency is measured at different loads. An efficiency of 91.3% is achieved at the rated power of 21 watts and a maximum efficiency of 92.5% is achieved at 16-watt output power. At 38-watt output power, the efficiency is lowered to 87.7% due to increased conduction losses.
Experimentally measured efficiency of the proposed converter.
5. Conclusion
A new topology of interleaved boost converter is presented in this study. Besides the well-known feature of ripple reduction/cancellation of the interleaved converters, the proposed topology has several additional advantages over the traditional interleaved boost converter. The analysis shows that traditional interleaved boost converter will undergo high duty cycle operation and reverse recovery problem, whereas the proposed converter can achieve the same voltage gain at appropriate duty cycle. The voltage stress on switches of the proposed converter is 260% less than that of traditional interleaved boost converter. An efficiency of above 90% is achieved which is considered good. These features make the proposed converter a more suitable candidate for renewable energy generating system where high step-up dc-dc voltage conversion is required.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
Acknowledgment
The authors would like to thank the sponsorship of the National Science Foundation of China (NSFC) (no. 51177147).
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