A New Approach to the Topological Design of Hybrid Circuits

A computer-aided topological hybrid layout-design procedure is proposed, that yields the wanted principal routing 
in the form of a geometrical planarization graph. A so-called grid-embedding of a circuit graph into the Euklidean 
plane enables us to observe all except one of the various technological constraints. The real problem is reduced to 
finding a proper arrangement of “nets” and “flocks” in the plane in order to meet the omitted cross-capacity 
constraint. The solution is accomplished by a constructive and implicit enumeration procedure, which is used within 
an interactive man-machine design process.


INTRODUCTION
In this paper we deal with a problem which is of central importance in the design of hybrid microelectronic circuits. The development of a hybrid circuit layout is a complicated and skilful task, and only a few attempts have been made to use a computer in the essential parts of the layout-design process.1,2,a We restrict ourselves only to that part of the twofold layout-problem, called topological design, which ends up in a principal realizable routing of the conductors without regarding the size, the shapes and the positions of the elements. The second subsequent step would be the topographical design, that definitely yields the geometrical layout.
Solving the topological layout-problem, several technological and user-imposed constraints have to be taken into account. We assume only one layer for the realization of the circuit in thick film or thin film technology. Therefore, no crossings between different conductors and no over-lappings between components are allowed. The linear order of the terminals of line elements and the oriented cyclic order of the terminals of ring elements must be observed. Boundary terminals must be realizable at the boundary of the substrate in an eventually prescribed order. A very useful but constrained freedom is the possibility of crossing a gap between two adjacent 181 terminals of a hybrid element by a limited number of conductor lines. According to Rose,4 this number is called the cross-capacity of the gap, while the fact itself.is referred to as the capacity-constraint.
The computer-aided solution of the topological hybrid layout-problem presented in this paper is accomplished by the following steps: ,6,7 1) MAPPING of the circuit into the circuit graph S. 2) GRID-EMBEDDING of S into the Euklidean plane R 2, generating a geometrical tlanarization graph G. The elements of G are arranged in R 2 by means of straight lines of an orthogonal grid. This helps in following the various constraints. Only the capacity constraint is not taken into account.

3) PLANARIZATION OF G, performed by
using the freedoms of rearrangement within the frame of the grid. A graph G is successfully planarized and then is called a feasible solution of the topological layout-problem, if the capacity-constraint is also observed. This step is the main part of the procedure. We propose an algorithm for the constructive and implicit enumeration of all possible "net"-arrangements, while the "flock"-arrangement will be done by hand by means of man-machine interaction.

CIRCUIT GRAPH S
Only topologically relevant features of a given circuit are modelled in the circuit graph S. We distinguish between line and ring elements depending on the component types actually used. 8  Each terminal is mapped into a unique vertex of S; Each terminal gap constrained by a crosscapacity equal or greater zero is modelled by an edge; all edges of a circuit element form a flock, which is the image of this element in S; -Each connection tree is mapped into a hyperedge, 9 called net, which connects all vertices of the terminals joined by the tree.  y). The x-limited subplane between two columns is called a column-band. The grid-embedding of a circuit graph S generates a planarization graph G (also called a grid-model) and is performed in two steps. At first, nets are assigned to different adjacent rows and flocks are assigned to disjunctive adjacent column-bands. The boundary net (no. 1)is fixedly assigned to the row 1. The other assignments can be done arbitrarily. This important freedom will be used in the next section for the planarization of G. Here we choose the "natural" assignment, i.e. flock is assigned to the column-band just after that of flock i-1 and net j is assigned to row ]. The second step is the definite fixing of the flocks and nets. See Figure 2 an an example. Basically, vertices of S are represented in G by grid.points and edges by straight lines between two adjacent columns. Each column contains at most one vertex. Linear and cyclic orders are realized by according sequences of columns in the grid. A dosed edge-train consists of a forwardrunning open edge-train and a closing two-pieces edge with a vertical section and a backward-running horizontal section. See for example the gridembedding of flock 3 in Figure 2. A uniform clockwise orientation of all closed edge-trains can be achieved by choosing in each case the backwardbelow the forward-running part. All vertices connected by a net lie in a row and can be linked together simply by a limited straight line that defines the living section of the net within its row. A cross-point of a living net and an edge represents a crossing of a conductor line and a terminal gap. Each crossing reduces the cross-capacit of the participated edge.
The planarization graph G is called a solution, because all constraints except the capacity-constraint are taken into account. In general, this leads only to an infeasible solution. Feasibility is possible if for every edge in G its actual capacity is not less than zero.

PLANARIZATION
The above mentioned freedoms can be used for planarizing the geometrical graph G. The question is whether a net-and flock-arrangement exists that yields a feasible solution which strictly satisfies all constraints. At the moment, this problem has been solved by an inter-active procedure, in which the designer proposes a flock sequence while the search for an appropriate net-arrangement is performed automatically by a constructive and implicit enumeration algorithm.
Starting with a given flock-arrangement we look  is the number of nets in the list and k is the "address" of this arrangement. As an example, for ] 4 we have 3! 6 different possibilities NN(4, 1) to NN(4, 6), which can be put in order in the way shown in Figure 3. These six net-arrangements derive from the two with/= 3 nets. Figure 3 shows the complete hierarchy, called solution-tree, for n 4 nets. Beginning with the root of the tree, which corresponds to the arrangement of only the one net N1, each net-arrangement and, hence, each solution can be reached by adding net by net to the actual arrangement. Each node of the tree itself represents a root of a subtree. If the root of a subtree is infeasible, every node of this subtree is infeasible, too. This fact helps in exploring the solution-tree implicitly, i.e. it is not necessary to inspect every node of the tree, if one can already determine "infeasibility" on a lower level ] < n.
The net-arrangement-procedure works in principle as follows: SIarting with the root on level ] 1 a depth-first-search on the solution-tree is performed, looking for feasible nodes. If an. infeasible node is  At the beginning and during the search global and local restrictions can be stated, which are based on a fact explained by means of Figure 2b: Net N6 is living in the column.band bounded by columns 5 and 6. The edge in this band has cross-capacity 0 and is incident to the nets N1 and Na. If N6 is arranged between NI and Na, the solution becomes infeasible. Hence, we restrict N6 not to be laid between N and N3. These simple restrictions lead to a striking improvement of the effectiveness of the netarrangement procedure. Figure 4 shows the result of a topological design of a circuit with 32 components (incl. 5