COMPUTER SIMULATION OF HYBRID INTEGRATED CIRCUITS INCLUDING COMBINED ELECTRICAL AND THERMAL EFFECTS

This paper describes the application of a modern general purpose network analysis programme SPICE2 for the electrothermal analysis of hybrid integrated circuits. Self thermal coupling effects are modelled using the non-linear dependent current and voltage source capability in this programme, together with thermal environment parameters obtained from a three-dimensional thermal analysis program. Although numerical results are given by a bipolar transistor, the method is also applicable to mono- lithic integrated circuits and to resistors with variable temperature coefficients as power dissipating elements.


INTRODUCTION
A typical hybrid circuit is of such complexity that both a simplified structural model and some analysis assumptions are necessary for a tractable representation of both electrical and thermal effects. Figure shows the structural model used here, for the case in which the power dissipating element is a semiconductor die of thickness te, with a bonding material of thickness tE attaching it to a substrate of thickness ts.
The most significant assumptions are as follows (these are essentially those of Reference 1): a) Heat transfer is primarily by conduction #; radiation and convection are neglected; L FIGURE 1 A semiconductor die of thickness e, attached to a substrate of thickness ts by a bond of thickness rE. The upper surface of the die is at a uniform temperature Tj, and the lower surface of the substrate at a temperature Ta(K.). b) A given material is assumed homogeneous and isotropic (constant thermal conductivity); c) All resistors are of negligible thickness and dissipate power uniformly over their area; d) The power dissipation Pe of a semiconductor die such as that of Figure 1 is uniform over the top surface.

STRUCTURAL THERMAL CHARACTERISTICS
For the semiconductor die and bond regions of Figure 1, lateral dimensions are normally much greater than the region thickness. Accordingly, heat flow is taken as vertical so that a thermal resistance analog may be used. The thermal resistance between the faces of the semiconductor die is then RSI te/keA K/watt (1) where kc chip thermal conductivity, watts/cm--K; tc chip thickness, cm.; A cross-sectional area, cm 2 In a similar manner, the thermal resistance due to the bonding region is REB tE/kEA K/watt (2) where the notation corresponds to that for Eqn. (1). However, the thermal resistance concept cannot be simply extended to the substrate as its temperature distribution is actually three-dimensional. A precise formulation 2 of this problem has been applied to the determination of the 'optimum' value of 0 for the constant angle heat spread model shown in Figure 2. Given the assumption that heat flow is confined to this pyramidal section, the correct theoretical expression for the surface-to-base thermal resistance is: Constant angle thermal resistance model for a chip of dimensions L X L on a substrate of thickness ts. Heat flow is assumed to take place in a truncated pyramid whose sides make an angle with the vertical.

Rcp
K/watt (3) ks L(L/ts + 2tan 0) Comparison with a precise computer solution a shows that this expression is in error by less than 10% for L/ts > .5 if 0 32. Since the dimensions of many practical designs satisfy this requirement, this is a useful method for calculating the temperature drop in the substrate. It should be noted that the values of 0 0 and 0 45--are seriously in error, and that thermal coupling to adjacent devices is assumed negligible.

Numerical Results
For a 2N3020 silicon NPN transistor, the values in Eqn (1) Thus, the overall thermal resistance from junction to ambient would be the sum of the three given above, or RjA 52.4 K/watt (4) Experimental measurements of Ro, using an HP 10023A temperature probe showed agreement with the substrate thermal resistance model. It may be noted that thermal conductivities do vary appreciably with temperature, s'6 so that model accuracy may be impaired for this reason. This is especially true for the extremely thin bonding region with its high temperature differential.

DEVICE THERMAL CHARACTERISTICS
The effect of device temperature changes upon the electrical characterisitcs of a bipolar junction transistor operating in the normal active mode may be represented by the model in the upper left corner of Figure 3. This has previously been applied to small-signal transistor equivalent circuits7; it is here characterized on a large-signal basis so that there are no restrictions on temperature changes or voltage levels. In this model,/xV is the change in base-emitter voltage for a change in device temperature ATj, and as the computer programme SPICE2 requires a power series representation for nonlinear controlled sources, one may write AVB alATj + az(/XTj) 2 +... (5) in which the coefficients al, as an are the Taylor ATj Tj-T a As the quantities al, a2 an involve partial derivatives of VBr (T) with respect to T at constant base current, a simple physical model s may be used (8) in which A is a constant dependent upon device materials and geometry, T is the device temperature in degrees Kelvin, and Ego is the band gap voltage for the semiconductor. For the particular case of silicon with Ego 1.11 volts and a typical value of VBE(Ta) 0.7 volts at Ta 300K., numerical values for al and a2 are al 1.88 x 10 -a volts/K a2 1.29 x 10 -4 volts/(K) 2 (9) with higher order an's being neglected over the useful temperature range of silicon semiconductors in this application.

COMPUTER MODEL
The results of Sections 2 and 3 may be combined to obtain a model for the SPICE2 programme which includes both electrical and thermal effects. The steady-state power dissipation for the device in Figure 3 is essentially P IcVcE watts (10) where the DC power dissipation in the input circuit is assumed negligible. This equation is represented in the computer model by using a dependent current generator whose current is numerically equal to P with the two arguments I c and VcE. 9 A resistor RjA is connected across this source, as given by Eqn. (4), so that using ATj P RjA (11) the voltage developed across this resistor is numerically equal to ATj. This voltage is, in turn, used as the argument for a dependent voltage generator which represents Eqn. (5).
Only one line of input data is required to specify each dependent source, so that implementing the thermal model is relatively simple.
The curves in Figure 3 show collector current Ic as a function of base-emitter voltage VBE for a type 2N3020 NPN transistor. For curve A, no thermal coupling is included, i.e., AVa 0. For curve B, thermal coupling is included, and the effect of the first-and second-order terms in Eqn. (5) is clearly visible. In each case, the basic bipolar transistor model in SPICE2 was used, with model parameters taken from the manufacturer's data sheet.

CONCLUSION
Through the use of the nonlinear dependent generator capability in the SPICE2 programme, hybrid networks may be analyzed including simultaneous electrical and thermal effects. Although the device thermal modelling may be applied to any element for which the necessary temperature data and/or physical models are availalbe, the modified thermal resistance concept used here is only applicable for restricted device dimensions. The analysis is also limited to steady-state temperature conditions, and does not permit thermal coupling between power dissipating elements, an effect which may be significant. '1