SMALL-SIGNAL AND NOISE MODEL DETERMINATION FOR DOUBLE POLYSILICON SELF-ALIGNED BIPOLAR TRANSISTORS

In this paper, noise characterization and modelitg of a double polysilicon self-aligned bipolar transistor are presented. The device has been characterized in terms of noise and scattering parameters by means of an original automatic noise figure measuring system only. Measurements have been performed over the 1-4 GHz frequency range and at different bias conditions. The extracted model refers to the performance of the. chip device since the package and bond parasitics have becn accurately de-embedded by proper calibration techniques.


INTRODUCTION
Consumer applications in the field of wireless communication systems (cellular phones, cellular data transceivers, local-and wide-area networks, etc.) at low microwave frequencies (up to 4 GHz) widely use silicon bipolar circuits due to the attractive features they offer in terms of performances, low cost technologies, chip count, and power consumption, which make them competitive alternatives to GaAs technologies. Today's advanced bipolar processes often use double polysilicon (i.e., polycrystalline silicon) self-aligned (PSA) schemes. They key issue is the selfalignment of the extrinsic base and the emitter, both of which are outdiffused and contacted with highly doped polysilicon layers separated by an oxide spacer.
The use of PSA technology allows for a remarkable increase of the common emitter current gain /3 and a smaller dependence of/3 itself on temperature as compared to conventional transistors. In addition, PSA processes drastically reduce the base resistance and the collector-base capacitance, thus improving the device performance in terms of gainbandwidth product, maximum oscillation frequency, and low power dissipation. Parasitics reduction also allows for scaling "down both the lateral and the vertical dimensions of the transistor, thereby obtaining ultra-submicrometer junction depths [1,2].  In the aim of achieving an in-depth knowledge of the performance of this bipolar structure, we have characterized and modeled a packaged PSA device over the 1-4 GHz frequency range and at different bias conditions. The measurements of the eight scattering parameters and the four noise parameters have been carried out using only an automatic noise figure measuring set-up whose configuration has been implemented according to an original methodology and proper data processing techniques developed in our Lab [3,4]. Since the characterization involves both scattering and noise parameters, we have extracted an accurate equivalent circuit model that includes noise sources.
To our knowledge, this is the first complete analysis reporting details on the microwave performance of a double PSA transistor. The results presented in this work are relevant to the preliminary part of an extensive experimental investigation (100 devices supporting 16 different topologies) on the influence of the geometrical size and shape of the PSA emitter upon the transistor performance. It is well known that small-geometry effects take place affecting device operation. Thus, only a careful and reliable characterization can provide the manufacturer clear information on the adjustment to be carried out on the relevant process parameters.(*)

IN-PACKAGE DEVICE CHARACTERIZATION AND EXTRACTION OF CHIP PARAMETERS BY DE-EMBEDDING
The chip device structure, whose schematic cross section is illustrated in Fig. 1, exhibits an effective emitter made out of 250 nm of N-poly and 50 nm of As-doped single crystal Si with an opening width of 200 nm. The intrinsic B-doped base thickness is 80 nm and the extrinsic base is contacted by P-poly, which is separated from the N-poly emitter contact by a sidewall oxide having a typical thickness of 300 nm. A Si-filled deep trench with self-aligned oxide cap isolation contributes to the reduction of the collector-base capacitance.
The device has been enclosed in a standard microwave-type package (100 mil square) to facilitate its handling and insertion into electronic equipment. The transistor terminal pads have been electrically connected to the metalized segments and to the grounding pattern of the package. From the enclosing body, the external leads provide a way of connecting the device to the circuit.
As a consequence, the package introduces a variety of parasitic elements that modify the device performance at microwave frequencies. Such parasitics have, therefore, to be identified in order to determine the performance intrinsic to the chip by applying a computational procedure known as de-embedding. That is, the chip characteristics are extracted by "peeling off" the scattering and noise correlation matrices of each parasitic element from the scattering and noise parameters referred to the external terminals, thus proceeding towards the inner circuit section until the chip configuration is reached. By doing so, the obtained measured values and the relevant model properties can be employed to provide feedback information for optimizing the chip manufacturing process. Knowledge of the parasitics features have been acquired through S-parameter measurements performed on special dummy loads, i.e., packages providing the open, short, and thru calibration layouts. By means of such measurements, it has been possible to extract an equivalent circuit that accurately models the effects introduced by the package (wire-bonding included) and its electrical contacts with the test fixture where the device is placed for testing. In The transistor chip model is a standard hybrid-or structure where the effects due to distributed base resistance and distributed capacitance between intrinsic base and collector region have been introduced for an accurate representation of the transistor performance at microwave frequencies.
By de-embedding the effects of the previously described parasitics network from the measured parameter values, we obtained a different set of measured scattering and noise parameters, which refer directly to the chip device performance. The latter parameter sets have therefore been employed in the extraction of the chip model at the bia condition Vce 5 V, Ic 2 mA.
The modeling procedure is based upon the minimization of the global error function, which accounts for the differences between the values of each measured and simulated parameter. It has been found that, for better final results, the optimum weights Wi to be attributed to the different scattering parameter error functions during optimization should take on the following values: Wll 3, W2 0.5, W21 1.5, W22 0.6 The optimization cycles have been performed using commercial software CAD packages. The value of the gm parameter stems from the application o the wellknown relationship gm Ic q/KT which is a good approximation for small-signal operating devices. The model so determined is reported in Fig. 3  A sensitivity analysis has been carried out on the above model to bring out the influence of each circuit element on all the scattering parameters. The incidence matrix so determined is not sparse, thus demonstrating that for bipolar transistors, it is impractical to use a decomposition approach, as it has been successfully employed in modeling low-noise GaAs and pseudomorphic HEMTs [5].
The model effectiveness has then been tested by determining the element value variations in the different bias conditions. All the model elements exhibit value trends in very good accordance with the physics-related predictions.
As far as the microwave noise performance is concerned, we refer to the representation in terms of the four noise parameters that appear in the well-known relationship F(Fs) F0 +. 4  In order to extract a noisy model, two fundamental noise sources have to be accounted for in modeling bipolar transistors, i.e., thermal noise sources and shot noise sources. The thermal noise is generated by the resistive elements representing losses in the base, emitter, and collector regions respectively, and it is calculated by associating the ambient temperature value to them. In the common emitter (CE) configuration, the shot noise is generated by the statistical fluctuations of the base and collector current values that are, to some extent, correlated to each other. The adopted noise model for the chip device is, therefore, that reported in Fig. 5. On the basis of this noisy equivalent circuit, the noise parameters are then calculated.
The physics-based relationships that allows for evaluating the amount of noise power generated by the above generators, including correlation, are as follows (lil2) 4KTB Re(Vll) 2qlaB (li212) 2qIcB (li2 i2"1)= 2qlcB + 2KTBYE1e where Ia, Ic are the dc values of the base and collector current, Yiie are the network admittance parameters in the CE configuration, and B is the frequency bandwidth that is assumed to be 1 Hz for spot noise measurements.
From the above equations, derived for conventional BJT's, we calculated the initial values of the noise sources and their correlation coefficient (at the above cited bias condition) that have subsequently undergone the optimization procedure in order to minimize the global error function. Such initial values are reported in Tab. 1, a). It has to be noted that the element values of the small-signal model have not been involved in the noise optimization procedure, which is quite different from the modeling technique adopted for HEMTs [5]. The optimum weights associated to the noise parameter error functions have found to be" WF0 42, Wln, 60, W/r0 0.7, WRn 1 The optimization results exhibit an excellent matching between the theoretically predicted and the simulated noise current source values, whereas the correlation coefficient changes remarkably from its initial value turning to be mostly imaginary. A subsequent noise sensitivity analysis has allowed a further refinement of the previously optimized values, thus obtaining the final results reported in Tab. 1, b). An interesting result of this sensitivity analysis is that the real part of the correlation coefficient has a negligible influence on all four noise parameters, which confirms the final value assessed by the optimization procedure for the above coefficient. The comparison between measured and modeled noise parameters is shown in Fig.  6. Such results show outstanding values of the minimum noise figure over the entire frequency range, thus suggesting the adoption of PSA transistors in low-noise amplifiers of receiver front-ends.
By testing the effectiveness of the noise model at the bias conditions V 5 V, I 1 mA, we have obtained the values of the noise current sources and their correlation coefficient as reported in Tab. 1, c). As can be seen, the noise generators still match the physics-based predictions with a value reduction close to 50%, whereas the correlation coefficient reduces its absolute value still maintaining a phase of 90.
We might, therefore, hypothesize that the behavior of this latter noise coefficient be the only one markedly influenced by the structural difference between a PSA and a conventional Si transistor. As discussed above, a more extensive analysis on a wide variety of this device type is in progress, whose results will be employed to assess these preliminary results and to support modifications of the analytical noise relationships.

CONCLUSIONS
A complete characterization and modeling study has been presented on a double polysilicon self-aligned bipolar transistor over the 1-4 GHz frequency range and at different bias conditions. The characterization involved determination of both the scattering and the noise parameter sets by means of a noise figure measuring set-up only.
To the aim of referring the measured performance directly at the chip reference planes, we applied an accurate de-embedding procedure to the experimental data of the packaged device. An equivalent circuit model has then been extracted that includes noise sources.
Such model exhibits distinguished performances that are going to be further assessed through in-progress extensive investigation on several PSA devices.