SBT Approach towards Analog Electronic Circuit Fault Diagnosis

An approach for the fault diagnosis of single and multiple faults in linear analog electronic circuits is proposed in this paper. The simulation-before-test (SBT) diagnosis approach proposed in this write up basically consists of obtaining the frequency response of fault free/faulty circuit. The peak frequency and the peak amplitude from the error response are observed and processed suitably to extract distinct signatures for faulty and nonfaulty conditions under maximum tolerance conditions for other network components. The artificial neural network classifiers are then used for the classification of fault. Networks of reasonable dimensions are shown to be capable of robust diagnosis of analog circuits including effects due to tolerances. This is a unique contribution of this paper. Fault computation time is drastically reduced from the traditional analysis techniques. This results in a direct dollar savings at test time. A comparison of the proposed work with the previous works which also employ preprocessing techniques, reveals that our algorithm performs significantly better in fault diagnosis of analog circuits due to our proposed preprocessing techniques.


INTRODUCTION
The fault diagnosis process in digital systems has successfully reached a point of automation; however, for analog electronic circuits the diagnosis approach relies heavily on the test engineer's experience and intuition.The detailed knowledge of the circuit operational characteristics is required for developing test strategies.Owing to this, analog fault detection and identification task is still iterative and time consuming.The present state in electronic circuit manufacturing has introduced analog and analog/digital hybrid circuits where the circuit under test is quite large.Hence a systematic approach to automate the fault diagnostic task in these circuits wherein intuition and experience may no longer be sufficient [1][2][3] is highly required.
Several researches [2,4,5] have addressed the issue of fault diagnosis of analog electronic circuits at the system board and chip level.The research areas in this domain [6] encompass computational complexity, automatic test pattern generation, and design for testing process.Analog fault diagnosis is complicated by poor mathematical model, component tolerances, nonlinear behavior of components, and limited accessibility to internal nodes of the circuit under test.The general analog diagnosis algorithm falls under two categories (simulation after test and simulation before test).Simulation after test diagnosis technique uses traditional artificial intelligence and reasoning methods.The disadvantage of this method is that it increases the time spent on diagnosis at the production time.On the other hand, the simulationbefore-test approach develops a fault data dictionary with which the test data is compared and the corresponding state of the system is reported.This approach, though requires more initial computation cost, can provide faster diagnosis at the production time.
The difficulties encountered in analog fault diagnosis make the use of artificial neural network (ANN) quite appealing.The research presented here attempts to exploit the signature analysis capabilities of artificial neural networks [7] to provide fault diagnosis with minimal computational cost.The proposed method is a form of SBT with ANN serving the role of the classifier [8].The SBT approach basically consists of obtaining the standard frequency response of the fault free/faulty circuit topology.The peak frequency and the peak amplitude from the error response are extracted and preprocessed to deduce distinct signatures to be fed into ANN for classification.The paper is organized as follows.Section 2 introduces the general analog circuit frame work.The proposed algorithm is given in Section 3. Section 4 details the preprocessor and ANN.The experiments results are demonstrated in Section 5. Section 6 covers with a brief discussion on the comparison of the proposed technique with certain notable contributions made in this area by the researches.Section 7 concludes the paper.

GENERAL TESTING FRAMEWORK
Figure 1 shows the basic diagnostic system for the circuit under test (CUT).A sinusoidal signal of the unit amplitude is applied to the CUT and the frequency response of the circuit is analyzed for faulty and nonfaulty circuital conditions.
The maximum and minimum limits of error amplitude of the faulty circuits at the appropriate test frequency are listed for all faults.Under faulty conditions if the output falls within these maximum limits suitable signature is fed into the ANN which is suitably trained for fault classification.

PROPOSED FAULT DIAGNOSIS ALGORITHM
(1) The transfer function model, G(s), of the CUT is derived for nominal value of the circuit components.(2) The frequency response of the CUT is simulated under different faulty conditions and peak frequency ω p peak amplitude M(ω p ) is obtained.This peak frequency will serve as the test frequency for fault diagnosis.(3) Obtain the extreme fault bounds for various faults at corresponding test frequencies, that is, finding the upper fault limit (X H ), with the faulty component at ±50% (R ± 50%R) and all the other network components at the maximum positive tolerance limit error magnitude is determined.Similarly the lower bound (X L ) is determined for the maximum negative tolerance value for the other network components.(4) The extreme bounds (X H and X L ) for each of fault conditions are stored in an array.(5) The CUT is tested at various test frequency and if the error magnitude lies within the corresponding predetermined limits, suitable signature is fed to the ANN classifier which does the fault classification.
The block diagram for the proposed approach is given in Figure 2.

Preprocessor
Owing to the presence of noise, a complete fault dictionary containing all feasible conditions cannot obviously be gen-  erated.This problem is solved by giving inputs to the neural network in terms of bits-a "0" is assigned if the value observed for a specific test frequency is out of bounds; a "1" is assigned if the value observed for a specific test frequency is within bounds.that is, if

Artificial neural network classifier
Artificial neural network can provide an adaptive mechanism for the pattern classification [9].They are capable of robust classification in following environments: ill-defined model, noisy input environments, and nonlinearity.In this paper, the back propagation network (BPN) structure [10] provides best results for the classification task.A comparison of five network architectures is outlined in [11].Many other works have also had success using the BPN network.Examples include classification of sonar targets [12], speech recognition [13], and sensor interpretation [14].Recent successes have applied ANNs to process fault detection in chemical processes [15].Direct applications of ANNs for fault diagnosis can be found in [16][17][18].Typical BPN have two or three layers of interconnecting weights.Figure 3 shows a standard two-layer BPN network topology.Each input node is connected to a hidden layer node.Each hidden node is connected to an output node in a similar fashion .This makes BPN a fully connected network topology. Here, the output neurons of artificial neural network, V i j weight from ith input neuron to jth hidden neuron, W jk weight from jth hidden neuron to kth output neuron, V 0 j weight from bias to jth hidden neuron, W 0k weight from bias to kth output neuron.
The supervised learning in BPN takes place by propagating the node activation function of input pattern to output nodes.These outputs are compared with the desired target values, and an error signal (δ) is produced.The network weights are adapted so as to minimize the error.The generalized delta rule does the weight adaptation given by Δ p ω i j = δ p j x pi , where is the learning rate, δ p j is the error at the jth node due to pattern p, x pi is the ith element of the output pattern p.The error signal for the output node is δ p j = (t p j − o p j ) f j (net p j ), where t p j and o p j are target and output values, respectively.The number of nodes in a layer and the activation function will affect the learning rate, the computational complexity, and the usefulness of the network for a specific problem wherein the best results always come from intuition and experience.

SIMULATION RESULTS
The feasibility of this method is validated through two benchmark circuits.The first circuit considered is a standard Sallen key bandpass filter circuit and the second circuit considered is a standard state variable filter circuit.Both single as well as multiple component fault scenarios are applied to this circuit and the results obtained are graphically plotted.

Sallen key bandpass filter circuit
The circuit shown in Figure 4 is the Sallen Key bandpass filter circuit [3,6] with the component values correspond to a nominal center frequency of 25 kHz.Each resistor has a tolerance of 5% and capacitor has a tolerance of 10%.The transfer function of the Sallen-key bandpass filter circuit is where To study the testability of the circuit, the frequency response is plotted for various fault conditions.We consider the case of only one test point, that is, the output node.The sensitivity of the output signal with respect to single and multiple faults along with the frequency response of the nominal circuit is given in Figure 5.
The test frequency for the single faults of the filter circuit is obtained by incrementing the faulty component at ±50% and obtaining the frequency response of the circuit.In the process, all the other components are kept at their nominal values.The test frequency for each of the fault conditions is given in Table 1.There are totally 2n single faults where n is the nunber of components in the circuit for which the sensitivity analysis is done.
For multiple faults, there are n (n−1)/2 double faults, n (n−1)/3 triple faults, and n (n−1)/4 of quadruple faults.Totally 11 fault conditions are analyzed.The fault component value is 50% higher than the nominal values.These faults are observed at the output node by plotting the frequency response.The frequency response of the Sallen Key bandpass filter under multiple faults is shown in Figure 6.The test results are shown in Table 2.The fault free case is given the ID number F 20 .

Obtaining the fault bounds for the various faults
To obtain the fault bounds for R 2 (fault ID-F 1 case), the test frequency is set to 24.1915 kHz.The resistor R 2 is incremented by 50% and other components R 3 and C 1 , C 2 are kept at −5% and −10% tolerant values, respectively.The sensitivity, S(R 2 ), which is the error in magnitude between fault-free circuit output and faulty circuit output, is determined.This number serves as the lower limit (X L ) of the fault.A similar approach is carried out for calculating the upper limit (X H ) on the sensitivity value by keeping R 3 at +5% and C 1 , C 2 at +10%.The above procedure is repeated for all fault conditions at the appropriate test frequencies.The limits are stored in an array which is given in Table 3.

Pattern classifier
Since the test pattern for the Sallen Key bandpass filter circuit has 20 inputs (19 faults plus 1 fault-free condition), the ANN has 20 neurons in the input layer and 5 neurons in the output layer.The 5 neurons in the output layer can classify a total of 32 faults (2 5 ) and will be sufficient for classifying 19 plus 1 possible condition in our work.The number of neurons in the hidden single layer is 12.So the ANN structure boils down to 20 : 12 : 5.For all faults F 1 through F 20 , the corresponding subscripts (1 through 20) indicate the fault IDs.The pattern for a specific fault is generated by testing the CUT at all test frequencies under permissible tolerances for other network components.The ANN is adaptively trained to update the weights and the bias by gradient descent method by the mean-square-error performance.For few randomly generated test patterns for the filter circuit, classifier results are shown in Table 4.The results agree well within the corresponding fault ID.
As a case study, for fault F 13 , X 9 , and X 13 carry a logical 1 whereas all the remaining neurons carry a binary 0. This means that the analog circuit when tested for all frequencies produce output voltage lying within the permissible limits only for the test frequencies 17.9845 KHz and 16.3929 KHz, respectively-this corresponds 2176 10 .The output of ANN for this condition has a high logical in Y 2 , Y 3 , and Y 5 remaining output neurons have low logical in Y 1 and Y 4 .This bit combination corresponds to 13 10 signifying F 13 condition.Similarly, we deduce ANN classifier inputs and outputs for all fault cases.A few more test cases, namely, F 9 and F 10 along with F 13 , is detailed in Table 5.

State variable filter circuit
The circuit shown in Figure 9 is the state variable filter circuit [19] with the component values corresponding to a nominal center frequency of 25 kHz.Each resistor has a tolerance of 5% and each capacitor has a tolerance of 10%.
The transfer function of the state variable filter circuit is To study the testability of the circuit, the frequency response is plotted for various fault conditions.We consider the case of three test points.The sensitivity of the output signal with respect to single faults along with the frequency response of the nominal circuit is given in Figure 10.
The test frequency for the single faults of the filter circuit is obtained by incrementing the faulty component at ±50% and obtaining the frequency response of the circuit.In the process, all the other components are kept at their nominal values.The test frequency for each of the fault conditions is given in Table 6.There are totally 2n single faults where n is the number of components in the circuit for which the sensitivity analysis is done.For multiple faults, there are n (n−1)/2 double faults, n (n−1)/3 triple faults, and n (n−1)/4 of quadruple faults.Totally 28 fault conditions are analyzed among which only 13 faults are observable.The fault component value is 50% higher than the nominal values.These faults are observed at the output node by plotting the frequency response.The frequency response of the state variable filter under multi-ple faults is shown in Figure 11.The test results are shown in Table 7.

Obtaining the fault bounds for the various faults
To obtain the fault bounds for R 2 (fault ID-1 case), the test frequency is set to 24.1915 KHz.The resistor R is incremented by 50% and other components R 3 and C 1 , C 2 are kept at −5% and −10% tolerant values, respectively.The sensitivity, S(R 2 ), which is the error in magnitude between fault-free circuit output and faulty circuit output is determined.This number serves as the lower limit (X L ) of the fault.A similar approach is carried out for calculating the upper limit (X H ) on the sensitivity value by keeping R 3 at +5% and C 1 , C 2 at +10%.The above procedure is repeated for all fault conditions at the appropriate test frequencies.The limits are stored in an array which is given in Table 8.

Pattern classifier
Since the test pattern for the state variable filter circuit has 23 inputs.The ANN has 23 neurons in the input layer and 5 neurons in the output layer.The 5 neurons in the output layer can classify a total of 32 faults (2 5 ) and will be sufficient for classifying all condition in our work.The number of neurons in the hidden single layer is 10.So the ANN structure boils down to 23 : 10 : 5.
The pattern for a specific fault is generated by testing the CUT at all test frequencies under permissible tolerances for other network components.The ANN is adaptively trained to update the weights and the bias by gradient descent method by the mean-square-error performance.
The classifier structure for the circuit and the training pattern for 100 epochs are shown in Figures 12 and 13  For few randomly generated test patterns for the filter circuit, classifier results are shown in Table 9.The results agree well within the corresponding fault ID.
As a case study, faults F 13 , X 13 , and X 14 carry a logical 1 whereas all the remaining neurons carry a binary 0. This means that the analog circuit when tested for all frequencies produce output voltage lying within the permissible limits only for the test frequencies 3.3422 KHz and 6.0320 KHz, respectively-this corresponds 1536 10 .The output of ANN for this condition has a high logical in Y 2 , Y 3 , Y 4 , and Y 5 , remaining output neurons have low logical in Y 1 .This bit combination corresponds to 15 10 signifying F 15 condition.
Similarly we deduce ANN classifier inputs and outputs for all fault cases.A few more test cases, namely, F 3 and F 21 along with F 15 , is detailed in Table 10.

RESULT AND DISCUSSION
In this section, a comparison is made with the size and performance of the proposed neural network to show the significance of the technique.To perform a diagnosis of the faults described in Section 5.1, for the Sallen Key bandpass filter circuit, the work presented in [6] requires a three-layer back propagation neural network.This network has 49 inputs, 10 first layers, and 10 second layers (49 : 10 : 10).Their trained network was able to classify only single faults.The work presented in [3] requires three-layer back propagation network with 5 inputs, 5 neurons in layer 1, and 1 neuron in the output layer (5 : 5 : 1).The trained network was able to classify only 8 single faults.The proposed neural network structure has 20 inputs, 12 first layers, and 5 second layers (5 : 12 : 15), and can classify 8 single faults and 11 multiple faults.The real advantage of preprocessing becomes evident when applied to more complex state variable filter circuit shown in Section 5.2.The work presented in [19] can classify 17 single fault scenarios including the fault-free condition.The proposed method can classify 23 fault scenarios, consists of 12 single faults, 10 multiple faults, and 1 fault-free condition.
The results of proposed method clearly indicate that through appropriate preprocessing of an analog circuit output, one can train a neural network to correctly diagnose all faults unless the circuit's outputs are similar for some fault cases.This study indicates that the proposed preprocessing techniques have a significant impact on analog fault diagnosis due to the selection of an optimal number of relevant features.This leads to neural network architecture with minimum size that can be trained and carry out fault diagnosis with a high degree of accuracy.The main contribution of this work is the formulation and solving of fault diagnosis problem completely in frequency domain.This work is novel in the sense that the classical frequency domain concepts and nonmathematical neural networks are brought together on a unified platform of fault diagnosis.Currently, one limitation of this approach is the amount of simulation-beforetest (SBT) process which must take place before.The method does not guarantee that in every case the faulty components will be identified.Some times the set of possibly faulty elements obtained by the method is larger than the really faulty elements.This can especially occur if ambiguity groups appear.Hence in general, the method gives correct results and works effectively as illustrated via numerical examples.

CONCLUSION
A frequency response approach for analog electronic circuit testability analysis is proposed in this paper.By performing the frequency response test of the CUT under faulty and nonfaulty conditions, test frequency for every category of faults is selected.Using suitable decision making preprocessor, the corresponding faulty signature is fed into the ANN which does the fault classification.The result of the proposed method applied to the Sallen key bandpass filter circuit and state variable filter circuit is quite encouraging.

Figure 5 :
Figure 5: Response of the single components faults at the output node.

Figure 6 :
Figure 6: Response of the multiple faults at the output node.

Figure 8 :
Figure 8: Performance plot for the classifier.

Figure 10 :
Figure 10: Response of the single faults (a) at node 1, (b) at node 2, and (c) at node 3.

Figure 13 :
Figure 13: Training performance plot for the classifier.

Table 1 :
Test frequencies of the single faults for test circuit.

Table 2 :
Test frequencies for the multiple faults for test circuit.

Table 4 :
Few random tested patterns of the classifier.Component value (R i in "Kohm", C i in nF)

Table 5 :
ANN inputs and outputs for test cases F 13 , F 9 , and F 10 .

Table 6 :
Test frequencies of the single faults (dashes mean no access to nodes).

Table 7 :
Test frequencies of the multiple faults (dashes mean no access to nodes).

Table 10 :
ANN inputs and outputs for test cases F 15 , F 3 , and F 21 .