We present a novel method to model the tracking behavior of semiconductor transistors undergoing across-chip variations in a compact Monte Carlo model for SPICE simulations and show an enablement of simultaneous N(N−1)/2 tracking relations among N transistors on a chip at any poly density, any gate pitch, and any physical location for the first time. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom's characterization on device's distance-dependent mismatch. Our method is very compact, since we do not use a matrix or a set of eigen solutions to represent correlations among N transistors.

1. Introduction

As semiconductor feature size decreases, the statistical variations in circuit’s characteristic, caused by statistical variations in semiconductor processes, become increasingly severe. There have been many studies on the characterization, simulation, and modeling of such statistical variations, especially on interdie and intradie/across-chip variations and device tracking behavior in recent years [1–9]. In a statistical description of a process, device, or circuit’s variability, one important aspect is the modeling of across-chip variations (ACV) or device tracking in a SPICE model. In this paper, we present a novel method to model the tracking behavior of semiconductor transistors undergoing across-chip variations in a compact Monte Carlo model for SPICE simulations, and show an enablement of simultaneous N(N-1)/2 tracking relations among N transistors on a chip at any poly density, any gate pitch, and any physical location for the first time. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom’s characterization on device’s distance-dependent mismatch. Our method is very compact, since we do not use a matrix or a set of eigen solutions to represent correlations among N transistors.

2. Modeling of FET’s Tracking Behavior2.1. Modeling the Effect of Polysilicon Density on FET Channel Length’s Tracking

Field effect transistor (FET) channel length’s tracking relations are impacted by differences in poly pattern density. Poly pattern density is defined as the percent of total poly area within a given area (say, an area of 200 μm × 200 μm), which is a relatively small area from a wafer polish viewpoint but is very large compared to the size of a transistor. For all poly densities (within an allowed range; say, between zmin=20% and zmax=80%), the standard deviation of a single transistor’s channel length is a constant (covering all lots), independent of the poly pattern density z around it. However, the tracking in channel length between two FETs is impacted by the difference between two poly density values around each of them. When two FETs have similar poly density values, their channel lengths are more likely to be the same on a given chip. On the other hand, when two FETs have different poly densities around each of them, their channel lengths are more likely to be different on a given chip. Quantitatively, a characterization goes like the following. For a group of N(≥2) FETs in a small area with a same gate pitch but different poly densities, (a) all FETs have the same nominal channel length L0, independent of poly density z around each FET,〈Li(zi)〉=L0,i=1,2,3,…,N,
where zi is the poly density around the ith FET; (b) all FETs have the same variance for channel length, independent of poly density z around each FET,〈[Li(zi)-〈Li(zi)〉]2〉=σuc2+σd2+σcm2,i=1,2,3,…,N,
where σuc is completely uncorrelated part of channel length variations, σcm is chip-mean (completely correlated) part of variations, and σd represents a partially correlated ACLV component that is associated with poly density’s change on a chip; (c) the tracking between the channel length Li of the ith FET and the channel length Lj of the jth FET, however, is a function of the difference between the poly density zi around the ith FET and the poly density zj around the jth FET, 〈[Li(zi)-Lj(zj)]2〉=f1(zi-zj),i,j=1,2,3,…,N,i≠j,
with two limiting values,〈[Li(zi)-Lj(zj)]2〉⟶{2σuc2ifzi⟶zj,2(σuc2+σd2)ifzi⟶zmin,zj⟶zmax.
Notice that (3) gives N(N-1)/2 tracking relations among N FETs. In (3) and (4), poly densities are bounded at both ends,zmin≤zi,zj≤zmax,i,j=1,2,3,…,N,i≠j.
Also in (3), f1(∆z) is a continuous and symmetric function of ∆z and increases monotonically with |∆z|. It is very important to characterize both single-device’s tolerance and the tracking/mismatch between two devices separately. It is a challenge to find a stochastic function which leads to tracking behavior (3) for three or more FETs (N≥3) simultaneously. A difficulty lies in this: how to net list the ith FET without entering all other FETs information into the model call for the ith FET? There are only a few solutions.

We use polysilicon density z as a model instance parameter in an FET’s compact model. The Monte Carlo model for improved ACLV modeling isLi=L0+G0σcm+giσuc+G1σdcosπ(zi-zmin)2(zmax-zmin)+G2σdsinπ(zi-zmin)2(zmax-zmin),i=1,2,3,…,N.
In (6) and in the rest of the paper, each of G0,G1,G2,G3,…,g1,g2,g3,… is an independent stochastic variable of mean zero and standard deviation one. For a pre-layout (i.e., schematic) FET model in which poly density is not known at net list time, zi can be a random value between zmin and zmax. Using Monte Carlo model (6), it is easy to see that requirement (1) is satisfied and so is requirement (2). Also using model (6), N(N-1)/2 tracking relations among N FET’s channel lengths are found to be 〈(Li-Lj)2〉=2σuc2+4σd2sin2π(zi-zj)4(zmax-zmin),i,j=1,2,3,…,N,
which depends on the poly density difference |zi-zj| only. Comparing (7) with (3), one gets an explicit expression of the function f1(zi-zj). We want to point out that there is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (6). The Monte Carlo model (6) applies to other device/circuit tracking/ACV problems in which tracking between any two devices/circuits among a group of devices/circuits is a function of the difference of two parameter values associated with the two devices/circuits.

2.2. Modeling the Effect of Gate Pitch on FET Channel Length’s Tracking

In a given semiconductor technology, there is a minimum gate pitch (pmin), which is related to the lithography print capability used for the semiconductor technology. Note that a gate pitch is the sum of poly width (i.e., FET channel’s design length) and poly-to-poly space. At the minimum gate pitch, poly width is typically at the minimum poly width for the given semiconductor technology. Besides a minimum gate pitch (pmin), other larger gate pitch values (say, twice of pmin, four times of pmin, etc.) are also allowed. At a given larger gate pitch, poly width can take several different values. In other words, even at a single transistor’s layout level, there may not be any relation between a gate pitch and a local poly density. Since poly pattern density is an averaged value over a large area of, say, 200 μm × 200 μm, gate pitch and poly density are treated as two independent quantities. Often, a semiconductor company characterizes the effect of gate pitch and the effect of poly density separately. A characterization of the single channel length’s tolerance and the tracking between two channel lengths goes like the following. For a group of N CMOS FETs within a small area (say, within an area of 200 μm × 200 μm), there is a fixed value z for poly pattern density, but these N CMOS FETs can have different gate pitches. Quantitatively, (a) all FETs have the same nominal channel length L0, independent of gate pitch p,〈Li(pi)〉=L0,pi≥pmin,i=1,2,3,…,N,
where pi is the gate pitch of the ith FET. (b) All FETs have the same variance for channel length, independent of gate pitch p,〈[Li(pi)-L0]2〉=σuc2+σp2+σcm2,pi≥pmin,i=1,2,3,…,N,
whereσpis a component of ACLV variation that is associated with gate pitch variations on a chip. And (c) the tracking between the channel length Li of the ith FET and the channel length Lj of the jth FET, however, is a function of the ratio between the gate pitch pi of the ith FET and the gate pitch pj of the jth FET, 〈[Li(pi)-Lj(pj)]2〉=f2(pipj),pmin≤pi,pj≤pupper,i,j=1,2,3,…,N,i≠j,
with two limiting values,〈[Li(pi)-Lj(pj)]2〉⟶{2σuc2ifpi⟶pjorbothpiandpj≥pupper,2(σuc2+σp2)ifpi⟶pmin,pj≥pupper,i,j=1,2,3,…,N,i≠j.
Note that (10) gives N(N-1)/2 tracking relations among N CMOS FETs. The Monte Carlo SPICE model for channel length isLi=L0+G0σcm+giσuc+σpG3cosF2(pi)+σpG4sinF2(pi),i=1,2,3,…,N,
with F2(pi)=πln[min(pi,pupper)/pmin]2ln(pupper/pmin). Using Monte Carlo model (12a)-(12b), one sees that requirement (8) is satisfied and so is requirement (9). Also using model (12a)-(12b), N(N-1)/2 tracking relations among N channel lengths are now〈(Li-Lj)2〉=2σuc2+4σp2sin2[12F2(pi)-12F2(pj)]=2σuc2+4σp2×sin2πln[min(pi,pupper)/min(pj,pupper)]4ln(pupper/pmin),i,j=1,2,3,…,N,i≠j.
Comparing (13) with (10), one gets an explicit expression of the function f2(pi/pj). There is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (12a)-(12b). The Monte Carlo model (12a)-(12b) applies to other device/circuit tracking/ACV problems in which tracking between any two devices/circuits among a group of devices/circuits is a function of the ratio of two parameter values associated with the two devices/circuits.

2.3. Modeling the Effect of Across-Field Distance on FET Channel Length’s Tracking

The same FET in multiple (N) copies of a large macro (say, a gate array) placed randomly on a chip will have the same poly density and the same gate pitch. Each FET has identical single-device tolerance (covering all lots). The tracking between any two FETs is a function of the distance between them. When two FETs are next to each other, their channel lengths are more likely to be the same (on a given chip). When two FETs are some distance apart, their channel lengths are more likely to be different (on a given chip). Further, when two FETs are separated beyond a correlation range, their channel lengths differ by a maximum amount statistically. Quantitatively, the characterization for a group of N FETs goes like this〈Li(xi,yi)〉=L0,i=1,2,3,…,N,〈[Li(xi,yi)-L0]2〉=σuc2+σaf2+σcm2≡σL2,i=1,2,3,…,N,〈[Li(xi,yi)-Lj(xj,yj)]2〉⟶2σuc2ifxi⟶xj,yi⟶yj,i,j=1,2,3,…,N,i≠j,〈[Li(xi,yi)-Lj(xj,yj)]2〉⟶2(σuc2+σaf2)if|xi-xj|≥Sx,|yi-yj|≥Sy,i,j=1,2,3,…,N,i≠j,〈[Li(xi,yi)-Lj(xj,yj)]2〉=f3(xij,yij),i,j=1,2,3,…,N,i≠j,withxij=xi-xj,yij=yi-yj,
where σaf is a component of ACLV variation that is associated with across-field variations on a chip. Notice that (14e) gives N(N-1)/2 tracking relations among N FETs. We use the physical location (x,y) of each FET as two model instance parameters. Our elegant and compact Monte Carlo model is Li=L0+G0σcm+giσuc+σafQx(xi;k)Qy(yi;k),i=1,2,3,…,N,
withQx(xi)=1+2cx2(G1,kcosπxi2Sx+G2,ksinπxi2Sx)+1-2cx2(G3,kcos3πxi2Sx+G4,ksin3πxi2Sx),Qy(yi)=1+2cy2(G5,kcosπyi2Sy+G6,ksinπyi2Sy)+1-2cy2(G7,kcos3πyi2Sy+G8,ksin3πyi2Sy),142≤cx≤122,142≤cy≤122,where (xi,yi) is the coordinate of the ith FET, and k is a group index. Notice that other FET’s locations are not needed when net listing the ith FET. Relations (14a) and (14b) on single FET’s channel length are satisfied. N(N-1)/2 tracking relations among N channel lengths are found from (16) and (17a), 〈(Li-Lj)2〉=2σuc2+2σaf2[1-hx(xij)hy(yij)],i,j=1,2,3,…,N,i≠j,
when Li and Lj belong to a same group (i.e., same k), and 〈(Li-Lj)2〉=2σuc2+2σaf2,i,j=1,2,3,…,N,i≠j,when Li and Lj belong to different groups. In (18a), hx(xij)=1+2cx2cosπxij2Sx+1-2cx2cos3πxij2Sx,hy(yij)=1+2cy2cosπyij2Sy+1-2cy2cos3πyij2Sy.
Once again, there is no matrix, no eigenvalues, and no eigenvectors in Monte Carlo model (16). N(N-1)/2 correlation coefficients among N channel lengths areC(Li,Lj)=1-〈(Li-Lj)2〉2σL2=σcm2+σaf2hx(xij)hy(yij)σL2,i,j=1,2,3,…,N,i≠j.
When both chip mean variation and uncorrelated variation are gone, the correlation coefficient becomes directly proportional to the product of hx and hy, C(Li,Lj)=hx(xij)hy(yij),whenσcm=σuc=0.
The spatial correlation function (21) is plotted in Figure 1. The parameter Sx (Sy) is the ACV correlation range in the x (y) direction, hx(±Sx)=0,hy(±Sy)=0.
The meaning of parameters cx and cy is revealed by these relations,hx(±12Sx)=cx,hy(±12Sy)=cy.
In terms of correlation coefficient, it says thatC(Li,Lj)={cx,whenσcm=σuc=0,|xij|=12Sx,yij=0,cy,whenσcm=σuc=0,|yij|=12Sy,xij=0.
Namely, parameter cx (cy) is the correlation coefficient at half the ACV correlation range Sx (Sy). For a given characterization of spatial correlation, the values of cx and cy can be chosen within the range of relation (17b) (see Figure 1). [If cx is smaller than 2/4, however, the ACV correlation function hx(xij) will become negative (which is unlikely physically) before the separation |xij| reaches the correlation range Sx.] When the separation |xij| is larger than the correlation range Sx, the ACV correlation function hx(xij) will become either negative or will increase with increasing |xij|. Thus, when two or more devices are separated more than an ACV correlation range, they should be placed into different groups.

Spatial correlation function (21) versus xij/Sx at yij=0.

At a smaller separation, tracking relation (18a) reduces to Pelgrom’s characterization on device’s distance-dependent mismatch [10],〈(Li-Lj)2〉≈2σuc2+(xij2+yij2)π2σaf2(5-42cx)4Sx2,
when Sx=Sy,cx=cy,|xij|≪2Sx/3π,|yij|≪2Sy/3π.

Namely, the variance of the channel length difference is the sum of a constant term and a second term which is proportional to the square of the separation between two devices.

2.4. Modeling Several ACV Effects on FET Channel Length’s Tracking Simultaneously

Combining the above solutions, we can model several ACV effects on FET channel length’s variations simultaneously. For example, for the following tracking characterization among N CMOS FET’s channel lengths:〈Li(zi;pi;xi,yi)〉=L0,i=1,2,3,…,N,〈[Li(zi;pi;xi,yi)-L0]2〉=σuc2+σd2+σp2+σaf2+σcm2≡σL,tot2,i=1,2,3,…,N,〈[Li(zi;pi;xi,yi)-Lj(zi;pi;xj,yj)]2〉=2σuc2+4σd2sin2π(zi-zj)4(zmax-zmin)+4σp2sin2πln(pi/pj)4ln(pmax/pmin)+2σaf2[1-hx(xij)hy(yij)]f3(xij,yij),i,j=1,2,3,…,N,i≠j,
withzmin≤zi,zj≤zmax,pmin≤pi,pj≤pmax,i,j=1,2,3,…,N,
our overall compact Monte Carlo model is Li=L0+G0σcm+giσuc+G1σdcosπ(zi-zmin)2(zmax-zmin)+G2σdsinπ(zi-zmin)2(zmax-zmin)+σpG3cosπln(pi/pmin)2ln(pmax/pmin)+σpG4sinπln(pi/pmin)2ln(pmax/pmin)+σafQx(xi;k)Qy(yi;k),i=1,2,3,…,N.N(N-1)/2 correlation coefficients among N channel lengths areC(Li,Lj)=1-〈(Li-Lj)2〉σL,tot2=1σL,tot2(σcm2+σd2cosπ(zi-zj)2(zmax-zmin)+σp2cosπln(pi/pj)2ln(pmax/pmin)+σaf2hx(xij)hy(yij)π(zi-zj)2(zmax-zmin)),i,j=1,2,3,…,N,i≠j.

3. Summary

We have presented, for the first time, a novel method to model simultaneous tracking (or, say, correlation) among multiple FETs (while undergoing ACLV) at any poly density, any gate pitch, and any physical location in a compact Monte Carlo model, suitable for SPICE simulations. Without using commonly used matrix representation and associated eigen solutions, we have shown a set of very compact Monte Carlo models which simultaneously give N(N-1)/2 tracking relations among N semiconductor transistors versus one or more environment parameters, such as poly density, gate pitch, and/or physical location. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom’s characterization on device’s distance-dependent mismatch.

Acknowledgment

The author would like to thank IBM management for support.

McAndrewC. C.Colin.McAndrew@motorola.comDrennanP. G.Unified statistical modeling for circuit simulationProceedings of the International Conference on Modeling and Simulation of Microsystems (MSM '02)2002715718McAndrewC. C.Colin.McAndrew@freescale.comDrennanP. G.Device correlation: modeling using uncorrelated parameters, characterization using ratios and differences3Proceedings of the NSTI Nanotechnology Conference and Trade Show2006698702WattsJ.LuN.BittnerC.GrundonS.OppoldJ.Modeling FET variation within a chip as a function of circuit design and layout choices3Proceedings of the NSTI Nanotechnology Conference and Trade Show20058792GattikerA.BhushanM.KetchenM. B.Data analysis techniques for CMOS technology characterization and product impact assessmentProceedings of the International Test Conference2006110SpringerS. K.LeeS.LuN.NowakE. J.PlouchartJ. O.WattsJ. S.WilliamsR. Q.ZamdmerN.Modeling of variation in submicrometer CMOS ULSI technologiesYeY.LiuF.NassifS.CaoY.Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughnessProceedings of the 45th Design Automation Conference (DAC '08)June 20089009052-s2.0-5154909801410.1109/DAC.2008.4555948LuN.lun@us.ibm.comModeling of spatial correlations in process, device, and circuit variations3Proceedings of the NSTI Nanotechnology Conference and Trade Show2008818821OnoderaH.Variability modeling and impact on designProceedings of the International Electron Devices Meeting (IEDM '08)2008701704LuN.lun@us.ibm.comWattsJ.SpringerS. K.Elements of statistical SPICE models3Proceedings of theNSTI Nanotechnology Conference and Expo (NSTI-Nanotech '09)2009616619PelgromM. J. M.DuinmaijerA. C. J.WelbersA. P. G.Matching properties of MOS transistors