Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions:
Three-dimensional integrated circuits (3D ICs) provide a promising solution to process scaling and heterogeneous system integration [
Many papers have proposed algorithm of test schedule optimization for 2D IC [
The purpose of this paper is to propose a test scheduling method for postbond 3D IC testing to determine the optimal test time and TAM width under the temperature constraint. Two optimization modes can be chosen: A thermal-aware test scheduling and TAM co-optimization method for 3D ICs. Two optimization modes are supported for different 3D IC configurations. Simplified and accuracy thermal resistance model for temperature estimation to speed up the optimization process.
Thermal-aware co-optimization is essential to decide the optimal TAM assignment and test scheduling. This paper shows the following three important key results. When the number of TAM is smaller than a threshold, the test time is When the number of TAM is larger than the threshold, the test time is Compared with the hard-die mode, soft-die mode produces more effective test cost reduction. DfT architecture of each core should be optimized together with the whole 3D IC.
This paper is organized as follows. Section
We assume that each core has the same test time, power, and TAM width in different temperatures. The power of the core in the test mode is higher than the function mode [
In our proposed technique, the whole test scheduling is divided into many
An example test schedule: (a) without temperature constraint and (b) with temperature constraint.
In this work, we assume that the heat sink is not used in production test for cost reduction. In production test, heat sinks and heat spreaders are not installed to save test cost. As a result, test scheduling must consider temperature constraint to avoid overheating in test mode. In this paper, we only consider the steady state temperature during optimization. This is because dynamic temperature can settle within milliseconds, which is shorter than a test session. We assume that the heat is only generated by the power consumption of cores under test, ignoring the power of TSV drivers, which are very few in numbers.
In the hard-die optimization mode, we are given a 3D IC which has totally
In the optimization process, whenever a new test scheduling is generated, its peak temperature has to be estimated. The peak temperature of a test schedule is the maximum temperature of every test session in the test schedule. Exact thermal simulation is very time consuming so a simple 3D IC temperature estimation is needed. In this work, we adopt the thermal resistance model [
The 3D IC is divided into a two-dimensional array of
(a) A
In our thermal model, the heat flow is assumed unidirectional, from bottom to top. Because I/O pins are accessed at the bottom of our 3D IC model, the heat can only be dissipated from the top of our 3D IC model. We assume the bottom of CUT is connected to a board, which has been heated by previous testing, so heat propagation to the bottom die is ignored. The peak temperature of a single tile stack in Figure
In our thermal model, we assume the thickness of each die is 50
Please note that our test scheduling technique is independent of the thermal model. We could include downward heat propagation to the board or also include the lateral heat propagation by adding more thermal resistances into our thermal model [
Our co-optimization tool supports two modes: hard-die mode and soft-die mode. The hard-die mode uses the greedy algorithm to minimize both the total TAM width and test time in the hard-die mode flow of Figure
The overall flow.
The soft-die mode is slightly different from the hard-die mode in the soft-die mode flow of Figure
There are four input files to our optimization tool. The first file provides the power information of each core in the design. The second file describes the floorplanning information such as the location of each core. The third file offers the test information, such as the number of scan chains, the number of test pins, and the number of test cycles. The last file provides the 3D IC thermal model, such as thermal resistances and environmental temperatures.
This is a simple First, we sort the cores in decreasing order according to its test time. The first core with the largest number of test time is scheduled into the first slot. Pick the next core and schedule it into the existing slots if it “fits”; otherwise, the core is scheduled to a new empty slot. In this algorithm, a core that fits a slot means both temperature and TAM constraints are met. Repeat step 3 until all cores are scheduled.
In soft-die mode, after the greedy algorithm, we use simulated annealing to refine the solution. The simulated annealing algorithm is described in Algorithm
begin Get an initialize Get an initialize temperature Set the temperature threshold Set the decay rate while for 1 ≦ if else end for end while
The value[
In soft-die mode, four types of perturbation are used in simulated annealing:
Swap perturbation.
The move-to-existing-slot perturbation moves one core to an existing slot that contains at least one test. Figure
Move-to-existing-slot perturbation.
Although the above two perturbations can potentially reduce the total test time, the simulated annealing might be stuck in a local optimum. Therefore, the move-core-to-empty-slot perturbation is used to escape the local optimum. Figure
Move-to-empty-slot perturbation.
For the fourth perturbation, the selected core
Resize perturbation.
In order to estimate the cost, we define a cost function
To normalize the test time and TAM width, we first perform a hundred random test schedulings. The denominators are the average number of test cycles and the average TAM of a hundred random test schedulings. The
To decide the :
Please note that in this paper, we only consider the postbond test so prebond test and die probing costs are not included. TSV interconnect test time is very short so it is ignored in our test cost.
In this paper, we show results of three 3D IC test cases, each of which consists of five dies, indexed from zero to four. Die number zero (#0) is placed at the bottom of the 3D IC and die number four (#4) is placed on the top. Although there is no heat sink in production test, the heat sink is supposed to be installed on the top die number four (#4) in the system. In 3D IC,
The first test case is a
The first test case.
Die | Circuit | Technology |
Die power (W) | No. of cores | No. of scan chain | No. of test pattern | TAM width |
Test time (No. of test cycles) |
---|---|---|---|---|---|---|---|---|
Die 4 | Logic | 180 | 36.0 | 9 | 15 | 130 | 17 | 76,440 |
Die 3 | Logic | 180 | 36.0 | 9 | 15 | 130 | 17 | 76,440 |
Die 2 | ARM9 | 180 | 6.0 | 2 | 20 | 300 | 22 | 210,000 |
Die 1 | SRAM | 90 | 0.65 | 25 | N/A | N/A | 2 | 425,984 |
Die 0 | DRAM | 32 | 0.3 | 1 | N/A | N/A | 2 | 500,000 |
Besides the first heterogeneous test case, we also handcrafted two
Tables
The second test case.
Die | Circuit | Die area (mm2) | Die power (W) |
---|---|---|---|
Die 4 | p93791 | 7.30 × 4.21 | 42.97 |
Die 3 | p22810 | 3.37 × 2.92 | 13.79 |
Die 2 | p34392 | 2.54 × 2.86 | 10.16 |
Die 1 | f2126 | 3.29 × 1.32 | 6.09 |
Die 0 | d695 | 1.33 × 1.97 | 3.63 |
The third test case.
Die | Circuit | Die area (mm2) | Die power (W) |
---|---|---|---|
Die 4 | t512505 | 4.92 × 4.95 | 34.08 |
Die 3 | a586710 | 3.72 × 3.69 | 17.22 |
Die 2 | q12710 | 2.99 × 2.79 | 11.65 |
Die 1 | h953 | 1.09 × 1.61 | 2.46 |
Die 0 | g1023 | 1.23 × 1.32 | 2.28 |
The ambient temperature is set to 25°C. The ambient resistance models the interface of 3D IC and the ambient environment. This parameter is decided by the package. In our experiment, we set it to 4°C/W, assuming a medium priced package. Users can change these parameters according to different situations. In addition, we have to add the temperature constraint to our optimization process. For our experiment, we set it to 90°C, which is the same as other papers in 2D IC test scheduling.
Figure
Results of case 1.
Figure
Figure
Figure
Figure
Figure
Results of case 2.
Figure
Results of case 3.
In Table
Results of soft-die mode.
Type | Case 1 | Case 2 | Case 3 | ||||
---|---|---|---|---|---|---|---|
|
1 : 1 | 10 : 1 | 1 : 1 | 10 : 1 | 1 : 1 | 10 : 1 | |
Hard-die mode | No. of test cycle | 1,823,944 | 882,200 | 1,216,486 | 1,181,825 | 86,509,578 | 86,509,576 |
Opt. TAM | 38 | 113 | 138 | 162 | 31 | 31 | |
Normalized test cost | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | |
| |||||||
Soft-die mode | No. of test cycle | 1,823,944 | 882,200 | 766,191 | 611,629 | 23,142,087 | 41,852,141 |
Opt. TAM | 38 | 113 | 138 | 162 | 30 | 27 | |
Normalized test cost | 1.00 | 1.00 | 0.69 (−31%) | 0.59 (−41%) | 0.54 (−46%) | 0.80 (−20%) |
To verify the accuracy of our thermal model, we use HotSpot to simulate our 3D IC and test schedules. In HotSpot simulation, we use exactly the same setup, such as core power, core location, thermal resistance of each die, and thermal resistance of ambient. Table
Temperature comparison for hard-die mode.
Test case | HotSpot (°K) | Proposed (°K) | Error |
---|---|---|---|
Case 1 | 362.10 | 362.68 | 0.16% |
Case 2 | 354.98 | 356.86 | 0.52% |
Case 3 | 361.47 | 362.89 | 0.39% |
A thermal-aware test schedule and TAM co-optimization technique for 3D IC are proposed in this paper. Two optimization modes are supported: hard-die mode and soft-die mode. We use a simplified thermal-resistance model to quickly estimate the temperature of a test schedule without simulation.
The results show that thermal-aware co-optimization is important to decide the optimal TAM width and scheduling. The optimal TAM width and test scheduling are very design dependent. Blindly adding TAM width does not necessarily reduce test time due to the temperature constraint. Another important conclusion is that soft-die optimization greatly reduces the test time so DfT architecture of each core should be optimized together with the whole 3D IC.
Possible future work includes the consideration of prebond test, more sophisticated thermal models, and more realistic cost model.