This paper presents some additional high input low output impedance analog networks realized using a recently introduced single Dual-X Current Conveyor with buffered output. The new circuits encompass several all-pass sections of first- and second-order. The voltage-mode proposals benefit from high input impedance and low output impedance. Nonideality and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement with theory.
1. Introduction
In the recent past, realization of configurable analog networks has assumed special significance for modern analogue signal processing applications. The feature is quite suited while designing analog blocks with easy configurability, so as to be employed in field programmable analog arrays (FPAAs). Simple analog blocks with this feature were reported earlier and further researched in most recent works [1–3]. Whereas configurability gives rise to the possibility of several electronic functions from a single topology, cascadability results in practical utility of analog blocks for designing more complex networks without additional coupling elements in form of buffers [4–6]. The most recent analog circuit topology benefits from these features by being suited for a number of first-order electronic functions and offering high input impedance and low output impedance [5]. The two features together are just another step towards reducing circuit components enabling portable high performance systems with ease for FPAA implementations [7, 8]. It may be noted that analog filters continue to appear in open literature as a potential analog block for larger subsystems [2–6, 9–12].
This paper presents additional first- and second-order all-pass filters with the features of high input and low output impedance. State-of-the-art floating simulators have been employed to overcome the drawbacks of passive inductors [13]. It may be noted that floating inductor simulators using current conveyors have been researched well in the literature [14–17]. Transformation technique has further been employed to realize simpler alternative with lesser circuit complexity. Extensive simulations are performed to validate the proposed theory, which not only justify the proposed theory but also provide advancement to the existing knowledge.
2. Additional First-Order All-Pass Filters
The symbol and CMOS implementation of newly developed second generation Dual-X Current Conveyor (DXCC-II) with buffered output are shown in Figure 1. A newly developed DXCC-II is characterized in matrix form by the following relationship:
(1)[IYIZ+IZ-VX+VX-VW]=[000010000100001000-100001][IX+IX-VYVZ].
The new additional voltage-mode first-order all-pass filter topology is shown in Figure 2. It may be noted that interchanging the positions of X+ and X- yields the topology of [5], a fact not mentioned therein. The given topology is characterized by the general transfer function for continual signals in “s” domain as
(2)Vo(s)Vi(s)=-Z2Z3Z4+2Z1Z2Z3-2Z1Z3Z4Z1Z2Z4+2Z1Z2Z3+2Z1Z3Z4.
(a) Symbol of DXCC-II with buffer, (b) CMOS implementation of DXCC-II with buffer [5].
Topology extension by interchanging X ports of a recent work [5].
Specialization of the impedances in Figure 2 yields missing circuits of voltage-mode first-order all-pass filters as listed in Table 1. The circuits of Filter 1 and Filter 2 use two passive components. In the circuit of Filter 1, Z2 and Z4 are retained with Z2 as a resistor and Z4 as a capacitor while open-circuiting Z1 and Z3. In the circuit of Filter 2, Z2 and Z4 are retained with Z2 as a capacitor and Z4 as a resistor while open-circuiting Z1 and Z3. No matching condition is required in both of the circuits of Filter 1 and Filter 2. In the last two circuits of Filter 3 and Filter 4 three components are used in each case. In the circuit of Filter 3, Z1, Z2, and Z3 are retained with Z1, Z3 as capacitors and Z2 as a resistor while open-circuiting Z4. In the circuit of Filter 4, Z1, Z2, and Z3 are retained with Z1, Z3 as resistors and Z2 as a capacitor while open-circuiting Z4. The circuits of Filter 1 and Filter 2 enjoy the advantage of single resistor control. The circuit of Filter 3 also enjoys the feature of single resistor control but is noncanonical. It also employs both capacitors in grounded form. The circuit of Filter 4 is canonical by employing single capacitor but requires matched grounded resistors. It is also to be noted that other useful first-order analog functions (e.g., lossy and loss less integrators, high pass filter, etc.) are also realizable from the modified general topology of Figure 2.
First-order voltage-mode all-pass filters.
Circuits↓
Choice of passive components
Filter type
Z1
Z2
Z3
Z4
Matching condition
Filter 1
Open circuit
R2
Open circuit
1/sC1
No
Inverting
Filter 2
Open circuit
1/sC2
Open circuit
R4
No
Noninverting
Filter 3
1/sC1
R2
1/sC3
Open circuit
C1=C3
Inverting
Filter 4
R1
1/sC2
R3
Open circuit
R1=R3
Noninverting
3. Second-Order Filters
Selection of the impedances in Figure 2 yields a circuit of second-order voltage-mode all-pass filter by retaining all impedances Z1, Z2, Z3, and Z4. The selection of impedances is Z1 and Z3 as capacitive reactance (Z1=1/sC1,Z3=1/sC3,resp.)Z2 as resistive, and Z4 is taken as inductive reactance (Z4=sL4). It is a well-known fact that real inductors are not used in integrated analog systems due to their bulky size, which became a motivating factor for the introduction of active-RC networks long back. In the circuit proposed here, simulated floating inductor [13] is used in place of the real inductor. The DXCC-II based circuit of [13] realizes a resistor less floating inductor. The new proposed voltage-mode second-order all-pass filter using simulated inductance (L4≡Lsim) is shown in Figure 3(a). Another circuit is obtained by interchanging the positions of the X+ and X- terminals and is shown in Figure 3(b). The transfer function of the proposed circuits of Figures 3(a) and 3(b) is given as
(3)Vo(s)Vi(s)=ks2LsimC1R2-2sLsim+2R2s2LsimC3R2+2sLsim+2R2,
where k=+1 for the circuit of Figure 3(a) and k=-1 for the circuit of Figure 3(b).
(a) Proposed second-order all-pass filter using simulated inductor. (b) Another circuit obtained by interchanging X ports.
The expressions for pole-ω0 and Q are given in (4) and (5), respectively:
(4)ω0=2C3Lsim,(5)Q=R2C32Lsim.
From (4) and (5), it is found that the Q can be tuned independent of ω0 by adjusting the value of R2.
Sensitivity figures for pole-ω0 and Q are given as follows:
(6)SC3ω0=SLsimω0=-12,SR2ω0=0,SR2Q=1,SC3Q=-SLsimQ=12.
From (6), the sensitivity figures for the proposed circuits are found to be less than or equal to unity in magnitude which implies good sensitivity performance.
It is now to be emphasized that inductance simulator value is as Lsim=(C/gm1gm2), where gm1 and gm2 are transconductance of transistors used in simulated inductor, which can be controlled by the gate voltages of those transistors [13]. Here, gmi(i=1,2) is the transconductance of the ith MOS transistor and is given as
(7)gmi=2μCox(WL)i(VGi-VTi),wherei=1,2.
By substituting the value of Lsim in (3), the transfer function becomes
(8)Vo(s)Vi(s)=ks2CC1R2-2sC+2R2gm1gm2s2CC3R2+2sC+2R2gm1gm2.
The expressions for pole-ω0 and Q are also modified and given in (9) and (10), respectively:
(9)ω0=2gm1gm2C3C,(10)Q=R2C3gm1gm22C.
Sensitivity figures for pole-ω0 and Q are now given as follows:
(11)Sgm1,gm2ω0=-SC3ω0=-SCω0=12,SR2ω0=0,SR2Q=1,SC3Q=Sgm1,gm2Q=-SCQ=12.
All the sensitivity figures given in (11) are still less than or equal to unity in magnitude, which suggests good sensitivity performance.
Another possible circuit design is to use frequency transformation method [18]. In frequency transformation, all the impedances are scaled by the frequency-dependent factor 1/s. Such an impedance-level scaling operation is quite appropriate, because this operation does not affect the transfer function. The motivation behind this scaling operation is that scaling inductive impedance sL by 1/s leaves the circuit with the resistor of the same value, R=L, and the inductor is eliminated. However, so as not to change the transfer function in the scaling operation, all components must be scaled by the same factor. Therefore, the three passive elements are, namely,
(12)ZR=R,ZL=sL,ZC=1(sC).
After transformation (1/s) yields the new components
(13)ZR′=Rs,ZL′=L,ZC′=1(s2C).
Such scaling actually results in a transformation of the elements: a resistor (R) becomes a capacitor of value “1/R,” an inductor (L) becomes a resistor of value “L,” and a capacitor (C) becomes a frequency-dependent negative resistor (FDNR) and is denoted by “D” and symbolized as four parallel lines. The resulting circuit after frequency transformation is shown in Figure 4(a). Another circuit is obtained by interchanging the positions of the X+ and X- terminals and is shown in Figure 4(b). Here, the active realization of FDNR using DXCC-II may be used [19]. The active realization of FDNR has the advantage of using a single active element and tunability by means of control voltage. The impedance function [19] is given for the ideal case [Z]=1/s2Deq=2/s2C2R for C1=C2=C.
(a) Proposed second-order all-pass filter using frequency transformation. (b) Another circuit obtained by interchanging X ports.
The transfer function of the proposed circuits of Figures 4(a) and 4(b) is given as
(14)Vo(s)Vi(s)=ks2C12R1R4-4sC2R4+4s2C32R3R4+4sC2R4+4,
where k=+1 for the circuit of Figure 4(a) and k=-1 for the circuit of Figure 4(b).
The expressions for pole-ω0 and Q are given in (15) and (16), respectively:
(15)ω0=2C3R3R4,(16)Q=C32C2R3R4.
Sensitivity figures for pole-ω0 and Q are given as follows:
(17)SC3ω0=-1,SR3ω0=SR4ω0=-12,SC2ω0=0,SC2Q=-SC3Q=-1,SR3Q=-SR4Q=12.
From (17), the sensitivity figures for the proposed circuits are all less than or equal to unity in magnitude which implies good sensitivity performance.
As an application of second-order voltage-mode all-pass filter, a sinusoidal oscillator producing two-phase signals is next given. The circuit is shown in Figure 5; it consists of a voltage-mode second-order all-pass filter and a unity gain inverter, with the output of the inverter being fed back to the input of the first stage. It may be noted that the inverter (gain=-1) is realized using DXCC-II itself with input and output at Y and X-, respectively. The system loop gain (defined as VOUT/VIN, Figure 5) is given by
(18)VOUT(s)VIN(s)=(-1)s2LsimC1R2-2sLsim+2R2s2LsimC3R2+2sLsim+2R2.
If loop gain is set to unity at s=jω, the circuit shown in Figure 5 can be set to provide two-phase sinusoidal oscillation with oscillation frequency as
(19)f0=1Π2LsimC3.
The circuit provides two voltage outputs VO1 and VO2. The voltage outputs marked in Figure 5 are related as VO1=-VO2.
Proposed voltage mode sinusoidal oscillator.
4. Nonideal Analysis
A nonideal DXCC-II is characterized by the following port relationship:
(20)[IYIZ+IZ-VX+VX-VW]=[0000αp0000αn0000βp000-βn0000γ][IX+IX-VYVZ].
Here, αp and αn are the current transfer gains from X+ and X- terminals to Z+ and Z- terminals, respectively, βp and βn are the voltage transfer gains from Y input terminal to X+ and X- terminals, respectively, and γ is the voltage transfer gain from Z+ terminal to W terminal (buffered output). However, these transfer gains are close to unity up to very high frequencies [20]. Using (20), the proposed circuits of voltage-mode second-order all-pass filter using simulated inductor as shown in Figures 3(a) and 3(b) are reanalyzed so as to yield the following voltage transfer function:
(21)Vo(s)Vi(s)=kγs2αpβpLsimC1R2-sLsimβn(1+αn)+R2βp(1+αp)s2LsimC3R2+sLsim(1+αn)+R2(1+αp),
where k=+1 for the circuit of Figure 3(a) and k=-1 for the circuit of Figure 3(b).
The expressions for pole-ω0 and Q are given as follows:
(22)ω0=1+αpC3Lsim,Q=R21+αnC3(1+αp)Lsim.
Active and passive sensitivity figures for pole-ω0 and Q are given as
(23)SC3ω0=SLsimω0=-12,SR2ω0=0,Sαpω0=αP2(1+αp),Sαnω0=0,SR2Q=1,SC3Q=-SLsimQ=12,SαpQ=αp2(1+αp),SαnQ=-αn1+αn.
Using (20), the proposed circuits of voltage-mode second-order all-pass filter using frequency transformation as shown in Figures 4(a) and 4(b) are reanalyzed so as to yield the following voltage transfer function:
(24)Vo(s)Vi(s)=kγs2αpβpC12R1R4-2sβnC2R4(1+αn)+2βp(1+αp)s2C32R3R4+2sC2R4(1+αn)+2(1+αp),
where k=+1 for the circuit of Figure 4(a) and k=-1 for the circuit of Figure 4(b).
The expressions for pole-ω0 and Q are given as follows:
(25)ω0=1C32(1+αp)R3R4,Q=C3C2(1+αn)R3(1+αp)2R4.
Active and passive sensitivity figures for pole-ω0 and Q are given as
(26)SC3ω0=-1,SR3ω0=SR4ω0=-12,SC2ω0=0,Sαpω0=αp2(1+αp),Sαnω0=0,SC2Q=-SC3Q=-1,SR3Q=-SR4Q=12,SαpQ=αp2(1+αp),SαnQ=-αn1+αn.
Equation (22) and (26) shows that the sensitivity figures are all less than or equal to unity in magnitude which implies good sensitivity performance. Sensitivity of filter parameters to current transfer gains will remain less than unity for the ideal value of current transfer gains which is equal to unity.
5. Parasitic Considerations
The next study on the proposed circuits is carried out for the effect of parasitics involved with the used current conveyor. It assumes special significance for evaluating the real performance of any analog circuit. The various parasitics involved with a typical current conveyor [21] are well known to potential readers and will only be reviewed briefly. The various parasitics of the DXCC-II used in the proposed circuits are port Z parasitics in the form of RZ//CZ, port Y parasitic in the form of RY//CY and port X parasitics. The proposed circuits are re-analyzed by taking into account the above parasitic effects. A re-analysis of the proposed circuit of voltage-mode second order all-pass filter using simulated inductor as shown in Figure 3(a) yields:
(27)Vo(s)Vi(s)=-s2LsimC1′R2′-2sLsim+2R2′s2LsimC3′R2′+2sLsim+2R2′,
where R2′=R2+RX-, C1′=C1+CX+, and C3′=(C3+CZ++CZ-).
From (27), it is clear that the parasitic resistances/capacitances merge with the external value. Such a merger does cause slight deviation in circuit’s parameters. It can be further observed from (27) that the order of transfer function of second-order all-pass filter is not changed. The modified expressions for pole-ω0 and Q with parasitic effects are also given as
(28)ω0=2C3′Lsim,(29)Q=R2′C3′2Lsim.
Next, it is seen from (28) that the pole frequency would slightly be deviated (in deficit) because of these parasitics. The expression showing the effects of parasitics on pole-Q is also given in (29). The pole-Q would also deviate slightly because of the parasitics. The deviation is expected to be small for an integrated DXCC-II.
6. Simulation Results
The new proposed circuits are verified through PSPICE simulations. The simulations are based on 0.5 μm, TSMC, CMOS parameters. Table 2 shows the dimensions of MOS parameters which are used in CMOS implementation of DXCC-II of Figure 1(b). The supply voltages used are ±2.5 V, VBB=-0.6 V, CC=0.06 pF, and IB=25μA. The proposed voltage-mode second-order circuit of all-pass filter using simulated inductor has been designed at the pole frequency of 15.92 MHz. For the circuit of voltage-mode second-order all-pass filter (Figure 3(a)) resistance used is R2=20 KΩ, capacitors used are of values C1=C3=1pF, and, for the resistor less floating simulated inductor, the dimensions of the NMOS transistors are W/L=2μm/0.5μm. The bias voltages are selected to be 0.78 V so as to obtain a resistance of 20 kΩ across each one of the MOS transistor. The capacitance C is set to 2 pF so as to realize a floating inductance of 0.2 mH. The gain and phase response of the circuit of Figure 3(a) are shown in Figure 6, which shows the pole frequency as 15.85 MHz with a percentage error of 0.44%. The usefulness of new circuits is to be especially emphasized keeping in view the design frequency which is quite high. The input-output waveforms for voltage-mode second-order all-pass filter are shown in Figure 7. The Fourier spectrum of output is shown in Figure 8. The THD is found to be 1.5% which is also moderately low. The plot of THD variation at output with the amplitude of the input voltage is shown in Figure 9. Furthermore, the circuit of second-order voltage-mode all-pass filter using FDNR (Figure 4(a)) is also simulated. The gain and phase response of the circuit of Figure 4(a) are given in Figure 10. The circuit of Figure 4(a) was designed using C2=10 pF, R4=4 kΩ, and, for the realization of resistor less FDNR, the dimensions of the NMOS transistor are selected as W/L = 4 μm/1 μm. The bias voltage is selected to be 1.2 V so as to obtain a resistance of 1.6 kΩ across the MOS transistor. The capacitances are set as CD11=CD12=50 pF and CD31=CD32=50 pF to realize FDNR1 (D1) and FDNR3 (D3), respectively. The theoretical pole frequency used in this design was 25.18 MHz. The simulated pole frequency was found to be 25 MHz, which is very close to the theoretical value and only 0.71% in error.
Dimensions of MOS transistors in DXCC-II of Figure 1(b).
Transistors
W (μm)/L (μm)
M1, M2, M4, M5, and M15–20
4/0.5
M3, M6–10
8/0.5
M11–14
32/0.5
M21, M22, M25, and M26
2.5/0.5
M27
10/0.5
M23, M24
50/0.5
M28
100/0.5
Gain (dB) and phase (deg) response of second-order voltage-mode all-pass filter of Figure 3(a).
Input/output waveforms at 15.92 MHz.
Fourier spectrum of output waveform at 15.92 MHz.
THD variation at output with signal amplitude at 15.92 MHz.
Gain (dB) and phase (deg) response of second-order voltage-mode all-pass filter of Figure 4(a).
The Monte Carlo analysis of the second order voltage-mode all-pass filter (Figure 3(a)) was next performed taking 5% Gaussian deviation in the each passive component (C1, R2, C3, and Lsim). The analysis was done for 5 runs. The gain and phase response with Monte Carlo analysis is shown in Figure 11 and time domain result for Monte Carlo analysis is shown in Figure 12. As depicted from Monte-Carlo analysis results, the proposed filter has good sensitivity performances.
Monte Carlo analysis of Figure 3(a) showing gain (dB) and phase (deg) response.
Monte Carlo analysis of Figure 3(a) showing output for 5 runs.
7. Conclusion
This work presents four additional voltage-mode first-order all-pass filters and second-order all-pass filters with high input and low output impedance in each case. The circuits are based on the recently introduced active element, namely, Dual-X Current Conveyor with buffered output. As an application of the second-order voltage-mode all-pass filter, a voltage-mode oscillator configuration is given. Nonideal analysis of the proposed circuits is performed, and parasitic considerations are also discussed. The proposed circuits enjoy good active and passive sensitivities. Simulations results are given to confirm the presented theory.
Acknowledgments
The authors thank Academic Editor for recommending this paper. At the time of paper submission, the article processing charges for the Journal were waived off.
BegP.KhanI. A.MaheshwariS.SiddiqiM. A.Digitally programmable fully differential filterKhanI. A.NahhasA. M.Reconfigurable voltage mode first order multifunctional filter using single low voltage digitally controlled CMOS CCIIKhanI. A.SimsimM. T.BegP.Reconfigurable continuous time current mode first order multifunctional filter using low voltage digitally controlled CMOS CCIIProceedings of the International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT '11)December 2011Aligarh, India582-s2.0-8485801931710.1109/MSPCT.2011.6150460MaheshwariS.Analogue signal processing applications using a new circuit topologyMaheshwariS.ChaturvediB.High-input low-output impedance all-pass filters using one active elementMaheshwariS.MohanJ.ChauhanD. S.Voltage-mode cascadable all-pass sections with two grounded passive components and one active elementSunY.SunY.SolimanA. M.Generation of current conveyor-based all-pass filters from op amp-based circuitsTsukutaniT.TsunetsuguH.SumiY.YabukiN.Electronically tunable first-order all-pass circuit employing DVCC and OTABiolekD.BiolkovaV.Allpass filter employing one grounded capacitor and one active elementBiolekD.BiolkovaV.First-order voltage-mode all-pass filter employing one active element and one grounded capacitorSaadR. A.SolimanA. M.On the systematic synthesis of CCII-based floating simulatorsPalK.Novel floating inductance using current conveyorsSedraA. S.SmithK. C.A second generation current conveyor and its applicationsKhanI. A.ZaidiM. H.A novel ideal floating inductor using translinear conveyorsKacarF.YesilA.Novel grounded parallel inductance simulators realization using a minimum number of active and passive componentsSchaumannR.ValkenburgM. E.KacarF.MetinB.KuntmanH.A new CMOS dual-X second generation current conveyor (DXCCII) with an FDNR circuit applicationZekiA.TokerA.The dual-X current conveyor (DXCCII): a new active device for tunable continuous-time filtersTlelo-CuautleE.Sánchez-LópezC.Moro-FríasD.Symbolic analysis of (MO)(I)CCI(II)(III)-based analog circuits