Active and Passive Electronic Components
Volume 2014 (2014), Article ID 769198, 14 pages
http://dx.doi.org/10.1155/2014/769198

Research Article

Reconfigurable Mixed Mode Universal Filter

Neelofer Afzal and Devesh Singh

Department of Electronics and Communication Engineering, Jamia Millia Islamia University, New Delhi 110025, India

Received 26 June 2014; Revised 13 September 2014; Accepted 19 September 2014; Published 20 October 2014

Academic Editor: Sudhanshu Maheshwari

Copyright © 2014 Neelofer Afzal and Devesh Singh. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

This paper presents a novel mixed mode universal filter configuration capable of working in voltage and transimpedance mode. The proposed single filter configuration can be reconfigured digitally to realize all the five second order filter functions (types) at single output port. Other salient features of proposed configuration include independently programmable filter parameters, full cascadability, and low sensitivity figure. However, all these features are provided at the cost of quite large number of active elements. It needs three digitally programmable current feedback amplifiers and three digitally programmable current conveyors. Use of six active elements is justified by introducing three additional reduced hardware mixed mode universal filter configurations and its comparison with reported filters.

1. Introduction

Current feedback amplifier (CFA) plays significant role in area of signal processing/generation because of its higher speed, higher slew rate, simpler circuit realization, and most importantly the independence of gain and bandwidth [1–3]. Introduction of digital control/programming in CFA has further boosted its functional flexibilities and versatility [1]. Programmable characteristic of analog block is essential for controlling the undesired parameter variation caused by temperature and process. Analog programming techniques are widely used in a number of applications [3–8] but the limitation on the allowable range of analog tuning voltage makes it inconvenient for low voltage applications. Hence, in these applications, the digital control is more attractive [9]. Digital programming techniques not only yields better accuracy in avoiding parameter race than their analog counterpart [10] but also offers additional advantages such as better noise immunity, power saving option [11], and most importantly the compatibility to modern mixed mode (analog/digital) systems.

Digitally programmable universal filters (DPUF) are versatile and cost effective from IC realization viewpoint. However, to be compatible to IC realization it should fulfill following two conditions. First, it must be reconfigurable to realize different filter functions (types) without any change in configuration. Second, all its parameters should be independently programmable to set desired frequency response. Obviously, the availability of mixed mode operation will further enhance the versatility of such DPUF.

This paper presents a novel reconfigurable voltage/transimpedance mode (VM/TIM) DPUF using three digitally programmable CFAs (DPCFA) and three digitally programmable second generation current conveyors (DPCCII). The proposed UF can be reconfigured digitally to realize all the standard second order filter functions, namely, lowpass (LP), highpass (HP), bandpass (BP), band reject (BR), and allpass (AP) at single output port. The proposed DPUF configuration is (1) fully programmable as all the coefficients of its transfer function are independently controlled, which makes its parameters, namely, pole frequency (), quality factor (), and gain () independently programmable (2) fully cascadable by virtue appropriate (low/high for voltage/current) input and (low for voltage) output port impedances (3) less sensitive to nonidealities and parasitic effects. Use of only two grounded capacitor makes the proposed UF suitable from integration [12].

This paper also introduces three additional reduced hardware DPUFs using “2–4” active elements. These DPUFs are designated as derived DPUFs because they are obtained by the reduction of active elements of reconfigurable DPUF. Obviously, reduction in number of active elements also decreases the features of these derived DPUFs accordingly. But still, these DPUFs (including reconfigurable DPUF) possess more number of features than that of reported DPUFs using equal or more number of active elements. This fact in turn justifies the need of six active elements in reconfigurable filter. One common drawback of second and third derived DPUF is the use of floating capacitors, which is less attractive for integration. However, new integrated circuit technologies are capable of implementing efficient floating capacitor as double poly layer capacitor [13].

This paper is organized as follows. Starting from the introduction, Section 2 presents brief introduction of DPCFA, Section 3 presents the realization of reconfigurable DPUF, Section 4 deals with the derived DPUFs, Section 5 presents the comparison, Section 6 discusses the nonidealities and mismatch effects, Section 7 deals with SPICE simulation, and finally, the paper is concluded in Section 8.

2. Overview of DPCFA/DPCCII

The concept of digital control in DPCFA/DPCCII is based on employing an -bit current summing network (CSN), which scales up (amplification) or scales down (attenuation) the current gain of conventional CFA/CCII [1]. Figure 1 shows the CMOS structure of 3-array DPCFA. The CSN consist of transistors M13–M24. Depending on the code-bit values , respective arrays are activated or deactivated to produce port- current. DPCFA consists of a voltage follower (VF) between port and . CMOS structure of VF follows the same circuitry as formed by transistors M1–M12. A DPCCII is equivalent to a DPCFA with output VF removed.

Figure 1: CMOS structure of DPCFA with gain (adopted from [1]).

Port relation of DPCFA is described by following transfer matrix

where denotes the decimal equivalent of applied -bit codeword . It is given as

where denotes the th bit of applied codeword. Parameter , , and denotes the nonideal gain transfer ratios. All these gain parameters are unity in ideal condition. Power integer denotes current attenuation in range “1 to ” while denotes current amplification in range “0 to ”. The concept of zero gain (for ; that is, all bits zero) is used for programming the generation of various filter functions (types). Figure 1 shows the DPCFA structure with gain . DPCFA structure with gain can be found in [1].

Figure 2 shows the symbolic form of DPCFA and DPCCII. It shows th DPCFA/DPCCII block with current gain and applied codeword .

(a)

(b)

Figure 2: Symbol of (a) DPCFA and (b) DPCCII.

3. Proposed Reconfigurable DPUF

The proposed VM/TIM DPUF is depicted in Figure 3. It uses three DPCFA, three DPCCII, eight resistors, and two grounded capacitors. The UF offers the following attractive features.

(i)Availability of mixed mode operation.(ii)Digitally controlled filter functions (type).(iii)All the filter parameters (, , and ) are independently programmable.(iv)High (low) impedance input port for voltage (current) signal and low impedance output port enables easy cascading for higher order filter realization without requiring any buffer stage.

In addition to this, use of only two grounded capacitors makes the proposed DPUF suitable for monolithic integration.

Figure 3: Proposed reconfigurable DPUF.

The mixed mode operation of proposed reconfigurable DPUF is given by the following output function:

where the numerator () and denominator () functions are given by

It is evident from (4a)–(4c) that all the coefficients of numerator and denominator functions are independently programmable by codewords “”. This also justifies the need of minimum six programmable blocks in proposed DPUF. Codeword “” provides independent programming of and (discussed below) whereas codewords “” programming the numerator coefficients, not only governs the generation of various filter functions in both the modes but also provide them the independently programmable gain factors too. Additionally, by setting codewords condition   ; high (low) pass notch response can be realized. Table 1 summarizes the codeword conditions, realized gain parameters, and component and input (if any) matching conditions for the realization of various filter functions. Only AP and BR response requires component matching constraint.

Table 1: Codeword combination and realized filter functions.

Filter functions
Codeword combination
Gain () in different modes
Component matching condition
Input matching condition
(for TIM only)

VM* ()
TIM# ()

HP

NO
NR

BP

NO
NR

LP

NO
NR

BR

AP

For VM is required; #for TIM is required; NR: not required.

Setting codeword condition modifies (4a)–(4c) as

Filter parameters and from (6) are given as

It can be seen from (7a)-(7b) that and of all the responses are independently programmable through codeword and , respectively. Codeword condition makes the parameters and independently programmable. Thus, independent programming of these two parameters also requires minimum three programmable blocks [14].

One additional advantage offered by reconfigurable and derived (to be described in next section) DPUFs is the downscale programming of pole frequency (7a). This is achieved by reversing the gain parameter “” of blocks 2 and 3 by “”. In this case pole frequency decreases with increasing codeword . This approach is useful for achieving low frequency operation without requiring large component values, which is not favourable from area viewpoint in ICs.

Equations (7a)-(7b) can be rewritten as

where and are defined as component dependent factor of and , respectively. It is given as

For and equal resistor values , (9a)-(9b) reduces to

Capacitance value may be set at design level for quality factor of value as given by (10b). It is required for maximal flat LP and HP response. On the other hand, higher -values, required for BP and BR are obtained by programming , which can be further increased by adding additional transistor arrays in CSN of block-1.

4. Derived Mixed Mode DPUF

This section introduces three additional mixed mode DPUFs using “2–4” DPCFA/DPCCII. These are obtained by modifying the reconfigurable DPUF. In all the cases output function is same as given by (3). For brevity of discussion, features of all these DPUFs are discussed together in comparison section and also all the equations in this section assume codeword condition .

4.1. First Derived Mixed Mode DPUF

The first derived DPUF, as depicted in Figure 4 is obtained by deleting the and blocks of reconfigurable DPUF. It uses three DPCFA, one DPCCII, six resistors, and two grounded capacitors. The following set of equations characterize the mixed mode operation of this DPUF:

It can be seen from (11a)–(11e) that this modification retains the programming feature of and only. Although it provides the gain programming of HP response, it completely misses the programming feature of filter functions (types). Thus, the generation of various filter functions depends on the proper combination of input variables as shown in Table 2. This configuration needs component matching constraints for realization of AP and BR response. Additionally, it requires input inversion for AP realization.

Table 2: Derived filter functions for various input combinations.

Filter functions
Input combination

Voltage
Current

HP

LP

BP

BR

AP

are negative for first derived DPUF, and show actual applicable input, and not applicable for second and third derived configurations.

Figure 4: First derived DPUF.

4.2. Second Derived Mixed Mode DPUF

Further deletion of block results in second derived DPUF (Figure 5). It uses two DPCFA, one DPCCII, four resistors, and two capacitors. This modification leads to one of the capacitor floating. The mixed mode operation of this DPUF is characterized by the following set of equations:

The modification renders with only and programming. This configuration does not need any component matching constraint but it requires input inversion for AP realization. Moreover, it realizes only BP and LP in TIM.

Figure 5: Second derived DPUF.

4.3. Third Derived Mixed Mode DPUF

Further deletion of block results in third derived mixed mode UF as shown in Figure 6. It uses only one DPCFA, one DPCCII, and minimum number of passive components. Characterizing equations of this DPUF are given as

It is evident from (13a)–(13e) that this DPUF is almost similar to the second derived DPUF. Only the feature it lacks is programming.

Figure 6: Third derived DPUF.

5. Comparison

The performance of the proposed DPUFs is compared in Table 3 with similar reported filters. For fair comparison, active elements used in various filters are also expressed in terms of equivalent number of followers, that is, total number of current plus voltage followers (CF/VF) (active element and its follower equivalent is given in footnote of Table 3). Comparison is based on the following important features.

Table 3: Performance comparison of proposed filter.

Reference, year/criteria
1
2
3
4
5
6
7
8
9
10
11
12

[22], 2006
Y
Y
N
N
N
N

1/1
CM
3
3DC-CCII
15 K

[23], 2009
Y
N
Y
N
Y
Y
2
2/0
CM
ALL
3DC-CDBA
45.9 K

[18], 2013
Y
Y
N
N
Y
N
4
2/0
VM
2
3DP-CCII , 2CDN
20 M

[19], 2002
Y
Y
N
N
Y
N
3
2/0
VM
2
4DP-CCII
0.28 M

[20], 2013
Y
Y
N
N
Y
N
12
4/0
VM
3
5DC-FDCC
2 M

[9], 2009
Y*
Y*
Y*
N
Y
N
6
2/0
VM
3
5DPCCII
1.56 M

[21], 2011
Y
Y
N
N
Y
N
3
2/0
VM
3
5DC-BOTA
3 M

[5], 2012

N
N

3
2/0
ALL
ALL@
(4SO + 2DO) OTA
2.87 M

[6], 2010

N
N
N
Y

NA
2/0
ALL
ALL
(3SO + 1TO + 1DO) OTA
1.59 M

[7], 2009

N
N
Y

NA
2/0
ALL
ALL
4OTA, 1DO-OTA
1 M

[8], 2009

N
N
Y

NA
2/0
ALL
ALL
4OTA
1.59 M

[16], 2003

N
N

NA
2/0
ALL
<4
4DO-CCCII
12.5 K

[17], 2004

N
N
N

7
2/0
ALL
ALL
(4SO + 1DO) CCII
112 K

[4], 2007

N
Y
Y

NA
2/0
ALL
4
(2SO + 2DO) OTA, 3SW
10 M

[15], 2013
Y
Y
N
N
Y
N

2/0
VM/TAM
3/3
5DCCDVCC
14 M

[14], 2014
Y
Y
N
N
Y
N

2/0
ALL
ALL
(3SO + 2DO) DPCCII
4 M

[1], 2013
Y
Y
Y
N
Y
Y

2/0
VM
ALL
4DPCFA, 2DPCCII
0.4 M

R. DPUF (Figure 3)
Y
Y
Y
Y
Y
Y

2/0
VM/TIM
ALL
3DPCFA, DPCCII
2.6 M

1st DPUF (Figure 4)
Y
Y
Y#
N
Y
Y

2/0
VM/TIM
4/4
3DPCFA, 1DPCCII
3–5.5 M

2nd DPUF (Figure 5)
Y
Y
N
N
Y
Y

1/1
VM/TIM
4/2
2DPCFA, 1DPCCII

3rd DPUF (Figure 6)
Y
N
N
N
Y
Y

0/2
VM/TIM
4/2
1DPCFA, 1DPCCII

Conditionally programmable, not digital control, two filter function in TAM, #for HP only, for current output only, for voltage input only, DC-digitally controlled, SO-single output, DO-dual output, TO-triple output, CDBA-current differencing buffer amplifier- (2CF + 1VF), CCII- (1CF + 1VF), CFA- (1CF + 2VF), -equivalent number of followers, BOTA-balanced output transconductance amplifier, and DCCDVCC-digitally current controlled differential voltage current conveyor.

(1) Independently programmable , (2) independently programmable , (3) independently programmable gain, (4) programmable filter types, (5) appropriate input port impedance that is, high (or low) for voltage (or current) input, (6) appropriate output port impedance, that is, high (or low) for current (or voltage) output, (7) total number of resistors, (8) total number of capacitors (grounded/floating), (9) number of operating modes, (10) number of filter functions generated in each mode, (11) number of active elements used and (equivalent number of followers in braces), (12) operating frequency (in Hz).

Table 3 clearly indicates the trade-off between the features obtained and the number of active elements used in reconfigurable and derived DPUFs. Obviously, number of features varies proportionately with the number of active elements used.

The potential performance of proposed reconfigurable DPUF (Figure 3) is obvious from Table 3 itself. One important feature, which is not available in any of the reported filter except that of [4] is the programming of filter functions (types). This makes proposed DPUF suitable for integration. Blocks , , and of proposed DPUF not only govern the generation of different “filter type” but also provide the independent gain programming. It is noteworthy that independently programmable numerator coefficients of (5a) are useful in many ways such as in adaptive filtering applications and in realization of low pass & high pass notch. On the other hand, filter of [4] uses three MOS switches (SW) for programming the filter types and hence, completely lacks the feature of gain programming. Furthermore, it uses analog technique for programming of and . Obviously, additional active elements will be required to incorporate missing features. It can be seen from Table 3 that all the digitally programmable filters except that of [14, 15] operate either in VM or current mode (CM) only. DPUF of [15] operates in VM and transadmittance mode (TAM) but it realizes three filter functions only and also misses the programmability feature of gain and filter type. Similarly, DPUF of [14] also misses number of features (nos. 3, 4, and 6). Operational transconductance amplifier (OTA) [5–8] and CCII [16, 17] based filter, however, operate in all the four modes but none of them are digitally programmable and also they lack a number of important features (Features-1–4). Apart from this, filters configuration of [6–8, 16, 17] belongs to distributed input topology; thus, they also need current matching constraints as the proposed DPUFs requires. Additionally, filter of [8] requires weighted current/voltage ratios and input (voltage) inversion constraint. OTA based filters [5–8] and that of [16] are considered here because the digital control (as given in [15]) can be easily incorporated in these structures by programming their bias currents. In terms of power consumption, proposed filter shows better performance than that of [7]. Whereas proposed DPUF dissipates 4.88 mW (at 2.6 MHz); filter of [7] consumes quite large power, 30.9 mW at 1 MHz. The proposed configuration, however, lacks in terms of power consumption to that of [5]. Almost at same operating frequency, [5] dissipates power of 1.57 mW only. Power consumption of [15] is also high (6 mW) but it operates at higher frequency of 14 MHz.

All the proposed DPUFs (reconfigurable as well as derived) realize four or all filter functions in VM at appropriate impedance (low) port while all reported VM filters excluding that of [1, 14] realize three or lesser number of functions at inappropriate (high) impedance port. DPUF of [1] not only uses three more followers but also misses the mixed mode operation and programming feature of filter type. Similarly, the DPUF of [14] also lacks number of features (3, 4, and 6). However, its component count is low. OTA based filters [4–8] also lacks in providing voltage output at appropriate impedance level.

Comparison of first derived configuration (Figure 4), using four active elements (11 followers), shows that it realizes four filter functions in both the modes but the mixed mode structure of [15] realizes only three functions using five active elements. Compared to the proposed DPUF, filter of [14, 16, 17] uses one and two less followers, respectively, and also they operate in all the four modes but this is due to the use of dual output DPCCIIs. Also, [14] needs an additional VF to take the voltage outputs. It is to be noted that if output DPCFA of all proposed DPUFs are made dual output, that is, by creating additional -terminal, all the proposed filters can be operated in all the four modes. DPUF of [9] using one less follower provides the gain programming feature, which is not present in proposed first configuration (except for HP reponse) but it suffers from number of constraints. Filter of [9] uses two filter configurations for programming all the parameters of realized three filter functions. But still, its programming is constrained by the fact that variation of one of the parameters (Gain, , ) makes either one or both of the remaining two parameters nonprogrammable, while no such constraint applies over any of the proposed DPUF.

Second derived DPUF (Figure 5) uses one floating capacitor, which is less attractive for integration. However, it needs only three active elements (8 followers) and realizes four filter functions in VM at low impedance port. On the other hand, reported VM filters [9, 15, 18–21] using almost equal or more active elements/followers realizes lesser number of filter functions at high (not desired) impedance port. Although DPUF of [18] needs six followers and two current division networks (CDN) only, it realizes only two filter functions at high impedance port (not desired). Obviously, it [18] needs additional active elements (more than two followers) to fill the gap. Similarly, CM DPUFs, which are expected to have simpler circuit structure also needs additional circuitry. CM DPUF of [22] using six followers needs additional follower stages to fill the gap of missing cascadability feature and to take the current outputs available in working impedances of filter circuit. Similarly, filter of [23] using nine followers needs additional circuitry for providing weighted replica of input current inputs.

The smallest proposed configuration, that is, third derived configuration (Figure 6) clearly shows the trade-off between number of active elements used and the obtained features. It provides only programming and thus, it is suitable for designing the channel select filters. DPUF of [11] provides same feature ( programming) and realizes three filter functions only but it uses three operational amplifiers, two CDNs, six resistors, and two floating capacitors.

The comparison presented herein verifies the fact that the features of DPUFs vary proportionately with the number of active elements used. Since all the proposed DPUFs show better or comparable performance to that of reported DPUFs using almost equal number of active elements/followers, it implicitly justifies the need of six active elements used in reconfigurable DPUF for obtaining offered programmability features.

6. Nonideal Performance and Mismatch Effects

This section discusses the effect of CFA nonidealities and effect of component and current mismatch over the performance of proposed DPUF.

6.1. Nonideal Analysis

Nonidealities of CFA results from (1) small error in unity transfer gains as described by (1) and (2) CFA parasitics.

The modified output function of UF using (1) is given as

where subscript “” denotes the effect of nonidealities over filter function. Modified numerator and denominator functions are given as

Modified and factor using (15c) are given as

Similarly, the gain functions of basic filter functions are given as

Thus, the active and passive sensitivities of , , and may be summarized as

where “” denotes various active and passive elements, that is, , , , resistances, and capacitances. It is evident from (17a)-(17b) that the sensitivity figures are within reasonable limit. Parameter sensitivity of all derived configuration except that of third DPUF also lies in the same range as given by (17a)-(17b). Sensitivity of both parameters ( and ) of third derived configuration follows (17a).

Second set of nonidealities include DPCFA parasitics. DPCFA (and DPCCII) have high valued parasitic resistance (or ) in parallel with low valued parasitic capacitance (or ) at port (or ) and a low valued series resistance at port . DPCFA consists of an additional (parasitic) low valued series resistance at port . To simplify the discussion, parasitic resistances at ports and are not considered as these are much greater than the external resistance of circuit.

Output function of reconfigurable DPUF under the parasitic effect is given as

where subscript “” denotes the modified component values and function under influence of parasitics. For brevity reasons, output function is not segregated in numerator and denominator functions.

Modified component values of (18a)–(18f) are given as

It can be seen from (18a) that number of parasitics are absorbed in external circuit components. Thus, they do not create any unwanted pole. Expressions enclosed within the braces of (18a) denotes those parasitic terms, which causes deviation from the ideal response of (5a), (5b) and (6) (braces are used in all other DPUFs to denote the same). Thus, in order to nullify the effect of these parasitic, the following constraint over component values are imposed

Since and are of order of few ohms only, lower limit over external resistor values are easily satisfied if it lies in range of few kiloohms (). On the other hand, parasitic capacitances and (of order of few picofarads) offer very high impedance at operational frequencies; thus, upper limit is also satisfied if resistor values lie in few tens of (the same argument holds for all derived DPUFs also).

It can be seen from (18a) that the equation consist of the following parasitic poles:

The corresponding pole frequency is too high to affect the circuit operation.

Thus, if conditions of (18c) are met, (18a) reduces to

where , .

Similarity of (18a) and (5a), (5b), and (6) are obvious. It can be seen from (18b) and (18e) that number of parasitics is absorbed in external components and hence, do not cause any problem.

Modified filter parameters for are given by

Similarly, the output function of first derived DPUF under the parasitic effect is given as

where , , , , , , , and .

Constraints over external component from (19a) are given as

Modified output function satisfying conditions of (19b) is given as

Modified filter parameters (for ) from (19c) are given as

In order to simplify the further discussion, parasitic resistance is not considered in 2nd and 3rd derived DPUFs as these are of order of few ohms only. Output function of second derived DPUF under the parasitic effect is given as

where , , , , and .

Component constraints from (20a) are given as

Modified output function satisfying conditions of (20b) is given as

Modified filter parameters (for ) from (20c) are given as

Output function of third derived DPUF under the parasitic effect is given as

where , , , and .

Component constraints from (21a) are given as

Modified output function satisfying conditions of (21b) is given as

Modified filter parameters (for ) from (21c) are given as

6.2. Mismatch Effect

It can be seen from Table 1 that the realization of BR and AP response is constrained by component matching conditions. Also, the realization of these responses in TIM requires current matching constraint. Thus, it is necessary to study the effects of component and current mismatch over the filter parameters.

Firstly, the effect of current mismatch is presented. Current matching condition demands for additional active element, for example, multioutput current follower (MOCF) or multioutput CCII (MOCCII). Thus, the effect of current mismatch can be easily predicted by the help of (15b). Modelling the error in copy of current signals , , and by , , and , respectively, we have , , and , where “” denotes the ideal output current of used active element. Under this condition, only (15b) modifies as

Thus, this modifies the gain parameter (16d) of filter only. Current mismatch does not affect and . The modified gain function is given by

Gain sensitivity with respect to , , and follows (17b).

Next, considering the effect of component mismatch, it can be seen from Table 1 that realization of BR and AP requires matching constraint . It is, however, to be noted that any mismatch in resistors , , , , and does not affect parameters and ((16a), (16b)); rather it affects the gain parameters ((16c), (16d)) only. For simplicity, error in filter parameters is discussed for only those components, which require matching constraints. Taking the example of VM LP response, its gain parameter from (16c) is given as

Matching condition requires . Assuming mismatch of such that , gain error is given by

Similarly, matching constraint over , introduces error in and as

where , is the mismatch in and , respectively. It is to be noted that mismatch effect is additive in case of while it is subtractive in case of ; that is, the effect of mismatch is lesser over -factor.

7. Simulation Results

Performance of proposed UF is verified using 0.25 μm TSMC parameters and supply voltage ±0.75 V with same transistor aspect ratios as given in [1]. Taking equal resistor values and capacitor values as  nF,  nF, results in  KHz, , and . Where, denotes the component dependent factor of gain (). Simulation results are shown for VM responses.

Pole frequency programming (in range 375 KHz to 2.7 MHz) as described by (7a) is performed by varying . Figures 7 and 8 show the programming for various responses for different values of gain and -factor. Parameter values are depicted in simulation results. Codeword programming of all the parameters are mentioned in Table 4. Table 4 shows the applied codeword along with its decimal equivalent and corresponding parameter values (in square brackets).

Table 4: Codeword programming of filter parameters.

Filter function
Codeword programming

Pole frequency ()
-factor ()
Gain ()

HP  

=  
=
NA
(001), 4(100), 7(111)
=  
=

LP  

=  
=
NA
(001), 4(100), 7(111)  
=  
=

BP  

=  
=

=  
=
(001), 4(100), 7(111) 
=  
=

BR  

[=]  
=
(001), 4(100), 7(111)  
=  
=
(001), 4(100), 7(111) 
=  
=

denotes nonzero codeword among , or .

Figure 7: Pole frequency programming of HP and LP.

Figure 8: Pole frequency programming of BP and BR.

Quality factor programming through as described by (7b) is shown in Figure 9 for BP and BR response at frequency and gain . Quality factor values are chosen depending on the type of response.

Figure 9: Quality factor programming of BP and BR.

Similarly, gain is programmed (Figures 10-11) using suitable codeword as indicated in Table 4. Power dissipation of proposed reconfigurable DPUF is 4.88 mW. It is obtained for BP response when all the codewords are set to 7(111).

Figure 10: Gain programming of HP and LP.

Figure 11: Gain programming of BP and BR.

Figure 12 shows the time domain behaviour of BP response with gain 16.4 dB; that is, for . It is obtained by applying 70 mV peak sine wave of frequency 2.7 MHz. Figure 13 shows the variation of the THD with respect to the applied sinusoidal input voltage. The THD values of the circuit remain below 3% for input signals up to 70 mV peak.

Figure 12: Time response of BP response.

Figure 13: THD variation with respect to input sine wave signal.

8. Conclusion

This paper presents a novel reconfigurable mixed mode DPUF. The proposed VM/TIM DPUF offers several attractive features: generation of all the standard filter function, reconfigurable filter type, independently programmable filter parameters (, , gain), full cascadability, and low sensitivity figures. In addition to this, use of only two grounded capacitors makes the UF suitable for monolithic implementation. Circuit constraints are discussed by presenting parasitic study and mismatch analysis.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgments

The authors would like to thank the Department of Electronics and Communication Engineering, Jamia Millia Islamia University, for providing valuable support. Authors are also thankful to the anonymous reviewers for their valuable suggestions.

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