This study proposes three new sinusoidal oscillators based on an operational transresistance amplifier (OTRA). Each of the proposed oscillator circuits consists of one OTRA combined with a few passive components. The first circuit is an OTRA-based minimum RC oscillator. The second circuit is capable of providing independent control on the condition of oscillation without affecting the oscillation frequency. The third circuit exhibits independent control of oscillation frequency through a capacitor. This study first introduces the OTRA and the related formulations of the proposed oscillator circuits, and then discusses the nonideal effects, sensitivity analyses, and frequency stability of the presented circuits. The proposed oscillators exhibit low sensitivities and good frequency stability. Because the presented circuits feature low impedance output, they can be connected directly to the next stage without cascading additional voltage buffers. HSPICE simulations and experimental results confirm the feasibility of the new oscillator circuits.
1. Introduction
Sinusoidal oscillators constitute an important unit in numerous electronic devices, including electronic instruments, measurement systems, telecommunications, power conversion control circuits, and signal processing applications [1]. For the past several years, the typical configurations of sinusoidal oscillators in a wide array of circuit systems have combined operational amplifiers (op-amp) and additional passive components. A variety of sinusoidal oscillators using an op-amp as the active device are available [2, 3]. However, the finite gain bandwidth product of an op-amp decreases the oscillator circuit performance. To overcome this problem, researchers have investigated current-mode circuit techniques for signal processing in the past decades because they offer the advantages of greater accuracy, wider bandwidth, and higher slew rate than their voltage-mode counterparts [4]. Previous studies present several implementations of sinusoidal oscillators employing current conveyors (CCs) and current feedback amplifiers (CFOAs) [5–8], and the literature contains numerous sinusoidal oscillators constructed with different types of modern active devices [9–12]. Since the introduction of OTRA in 1992, it has become an important building block in analog circuit designs [13]. Subsequent development led to two high-performance CMOS OTRA realizations [14, 15]. OTRA can also be implemented using commercially available ICs [16], and has sparked interest in the design of OTRA-based analog signal processing circuits. Several oscillator circuits based on OTRAs have been presented [17–21]. To our knowledge, the first reported oscillator circuits using OTRA as the active device appeared in [17]. That study first introduced three single OTRA-based oscillator circuits and then four additional topologies using two OTRAs. However, the main disadvantage of these circuits is that they require excessive active devices and passive components. To overcome this problem, an improved topology built with a single OTRA, three resistors, and two capacitors was subsequently reported to reduce the component count [18]. Recent research presents an OTRA-based oscillator with noninteractive control [19]. However, that design suffers from complex circuitry involving two OTRAs, three resistors, and three capacitors. A literature review presents other types of sinusoidal oscillators, such as quadrature oscillators and multiphase oscillators, that use OTRA as the active device [20, 21]. Previous study revealed that an available method for generating quadrature oscillators is based on the cascaded all-pass filters technology [20, 22, 23]. Although single OTRA-based sinusoidal oscillators appear in previous reports, a number of effective topologies are missing in the literature. Therefore, the main purpose of this paper is to add three unpublished schemes to this list. One OTRA with a few passive components is required for the three topologies in this study. Because the OTRA-based application circuits got more and more attentions, we believe that these brand-new circuit configurations can be a good alternative to exploit OTRA for the design of sinusoidal oscillators. To illustrate the novelty of the proposed topologies, comparisons of various solutions are shown in Table 1. It should be noted that among the existing circuits, the proposed oscillators in this study feature the following benefits: (1) fewer or the same number of active devices and passive components is used; (2) independent control on the oscillation condition (oscillation frequency) without affecting the oscillation frequency (oscillation condition); (3) low active and passive sensitivities; (4) good frequency stability; (5) insensitive to the parasitic parameters; and (6) without an additional buffer for cascading applications. This paper is organized as follows. Section 2 first introduces the active OTRA device and then explains and analyzes the proposed circuits. Section 3 investigates the nonideal effects, sensitivity analysis, and frequency stability of the proposed circuits. Section 4 describes how examples were made for conducting simulation and experimental tests. Section 5 presents conclusions.
Comparisons among various sinusoidal oscillators.
Topology
Component numbers and passive component types
Classification of oscillator
Independent control of OC and OF
Signal output mode/buffer circuit requirement
Circuit implement technology
CCII-based [5]
CCII × 1resistor × 3(grounded)capacitor × 2(only one grounded)
SSO
YesOC: by ROF: NA
VM/Yes
Commercial ICs
CFOA-based [8]
CFOA × 1resistor × 3(only one floating)capacitor × 3(grounded)
SSO
YesOC: NAOF: by R
VM/No
Commercial ICs
CDBA-based(Topology a in Figure 2 of [9])
CDBA × 1resistor × 2(floating) capacitor × 2(only one grounded)
SSO
NoOC: NAOF: NA
VM/No
Commercial ICs
FTFN-based [10]
FTFN × 2resistor × 4(only one grounded)capacitor × 2(grounded)
The OTRA design concept originated from the commercially available Norton amplifier [24, 25]. However, the Norton amplifier has not gained considerable attention because commercially products do not provide a virtual ground at the input terminals and they only allow the input currents to flow in one direction. These adverse conditions limit its applications. Therefore, an improved design was suggested and renamed as operational transresistance amplifier (OTRA) [13]. The OTRA is a trans-impedance type active building block with two current input terminals (I+ and I-) and a voltage output terminal (Vo), which means that the input currents control output voltage through a transresistance gain. Figure 1 shows a circuit diagram of the OTRA used in this study. Its terminal relationships can be defined by (1), where Rm represents the transresistance gain. In the ideal case, the transresistance gain Rm approaches infinity and the two input currents are forced to be equal. However, this would only happen when OTRA is used in closed feedback loop and the infinite feedback loop gain ensures this. Since the input terminals of OTRA are internally grounded, this active device is free from numerous parasitic effects [26]. Another advantage of using OTRA to design analog circuits is that it is possible to obtain very accurate transfer functions in cascading applications [20]:
(1)[V+V-Vo]=[000000RmRm0][I+I-Io].
OTRA circuit diagram.
Figure 2 depicts a feasible CMOS OTRA consisting of a differential current controlled current source (DCCCS) followed by a voltage buffer [15]. The DCCCS unit in this figure is based on transistors M1 to M12, and M13 to M20 form the voltage buffer. Furthermore, the OTRA can be easily implemented using commercially available ICs with a configuration consisting of two AD844ANs [16] (Figure 3). If terminal Tz of the second AD844AN is an open circuit, the precise behavior of an ideal OTRA can be determined. Because the AD844AN IC is widely used in a variety of analog circuits, the implementation depicted in Figure 3 provides a viable means with which to implement an OTRA even though such a device is not currently available.
CMOS implementation of OTRA.
OTRA constructed using commercially IC AD844ANs.
Figure 4 shows the proposed new oscillators. Each circuit consists of a single OTRA and a few passive components. Since the minimum passive component sinusoidal oscillators have received much interest in the literature [27, 28], this study first introduces a 2R+2C topology to fulfill the minimum RC component design (Figure 4(a)). Assuming an ideal OTRA characterized by (1), routine circuit analysis yields the characteristic equation expressed in (2). Equations (3) and (4) determine the oscillation condition and oscillation frequency, respectively. The oscillation condition and oscillation frequency cannot be independently controlled on this circuit because it is a minimum RC oscillator:
(2)S2C1C2+S(G1C2+G1C1-G2C1)+G1G2=0,(3)G2G1-1=C2C1,(4)ωo=G1G2C1C2.
Circuit diagrams of the proposed single OTRA-based sinusoidal oscillators.
To achieve independent control of the oscillation condition without affecting the oscillation frequency, the second topology employs one OTRA with three resistors and two capacitors (Figure 4(b)). Equations (5) to (7) derive the expressions of the characteristic equation, oscillation condition, and oscillation frequency for this circuit. Among them, G1, G2, and G3 represent the corresponding admittances of the resistors R1, R2, and R3, respectively. Equations (6) and (7) show that the admittance G3 can control the oscillation condition without affecting the oscillation frequency:
(5)S2C1C2+S(G1C1+G2C1+G3C1-G1C2)+G1G2=0,(6)1+G2G1+G3G1=C2C1,(7)ωo=G1G2C1C2.
It is also possible to achieve independent control of the oscillation frequency without affecting the oscillation condition. In this case, Figure 4(b) shows that changing the resistor R3 to be a capacitor C3 yields the third topology, shown in Figure 4(c). Routine circuit analysis shows that the characteristic equation, oscillation condition, and oscillation frequency of this circuit are expressed as
(8)S2C1(C2+C3)+S(G1C1+G2C1-G1C2)+G1G2=0,(9)1+G2G1=C2C1,(10)ωo=G1G2C1(C2+C3).
This oscillator can be considered a single capacitor-controlled oscillator (SCCO) because the oscillation frequency can be controlled independently by C3. The presented scheme in this study provides a more compact circuit topology than the previous design (single capacitor-controlled oscillator) reported in [17]. However, typical single capacitor-controlled oscillators cannot provide an excellent tuning capability for the oscillation frequency. To attain a high tuning capability of the oscillation frequency, a tunable capacitor simulated circuit can be applied to overcome this problem [29]. Compared with the topologies reported in [17] [Figures 3(b) and 3(c)], the proposed oscillators use relatively few passive components to realize the topologies for the independent control of the oscillation condition and oscillation frequency. Because OTRA-based application circuits have received more attention in recent years, the proposed oscillator circuits can serve as practical designs for apply in the OTRA circuit systems.
3. Nonideal Analysis of the Proposed Circuits
This section considers several nonideal characteristics to determine the influences of nonideal effects on the proposed circuits. According to the datasheet [30], show that an AD844AN IC can be modeled as a positive second-generation current conveyor (CCII+) cascading a voltage buffer with inherent parasitic resistances and finite tracking errors. Figure 5 reveals a more sophisticated circuit model of the OTRA (Figure 3), where Rx and Rz are the terminal parasitic resistances. In this design, Rx is on the order of several tens of ohms, whereas Rz is in the range of a few mega-ohms. β represents the current tracking error factor from terminal Tz with respect to the inverting terminal. The AD844AN datasheet indicates that the standard values of these parameters are β=0.98, Rx=50Ω, and Rz=3 MΩ. Figure 5 includes the resulting expressions of the related currents. The parasitic resistance at the noninverting terminal and voltage tracking error effect between the inverting and noninverting terminals of CCII+ both disappear in the circuit model because of the ground connection at the noninverting terminal for each CCII+.
Equivalent circuit model of the OTRA (Figure 3) with nonideal and parasitic effects.
After applying the nonideal OTRA equivalent circuit model to the proposed circuits shown in Figure 4, tedious derivations lead to the following modified characteristic equations, oscillation condition, and oscillation frequency. The characteristic equation of Figure 4(a) becomes
(11)S2(C1C2(β+GzGx))n+S(βG1C1+βG1C2+G1GzGxC1+G1GzGxC2nnnnnnnnn+2G2GzG2+GxC2-βG2GxG2+GxC1)+(βG1G2GxG2+Gx+G1G2GzG2+Gx)=0,
where Gx and Gz represent the corresponding admittances of the parasitic resistances Rx and Rz, respectively. The modified oscillation condition and oscillation frequency are
(12)G2Gx(1+k)G1(G2+Gx)=C1+C2C1-2kC2(13)ωo′=G1G2GxC1C2(G2+Gx)=GxG2+Gxωo.
The parameter k is defined as
(14)k=GzβGx.
Equations (12) and (13) reveal that the nonideal current tracking error β and parasitic admittances Gx and Gz influence the oscillation condition and oscillation frequency. However, the influence of the parameter k can be ignored because the parasitic admittance Gx is much larger than Gz in magnitude. Note also that the parasitic admittance Gx slightly changes the oscillation frequency on this circuit. This slight deviation can be compensated for by selecting Gx≫G2 to minimize the influence on the circuit. Utilizing (13), the active and passive sensitivities of the circuit (Figure 4(a)) are
(15)SG1ωo′=SG2ωo′=-SC1ωo′=-SC2ωo′=12,SGxωo′=12(G2G2+Gx),Sβωo′=SGzωo′=0.
For the condition Gx≫G2, SGxωo′=0. The circuit exhibits a good sensitivity performance because all active and passive sensitivities are less than unity in magnitude. For Figure 4(b) circuit, the modified characteristic equation is
(16)S2((1+GzβGx)C1C2)+S(GzβGx(2G2C2+G1C1+G2C1+G3C1)G1G1C1+G2C1+G3C1-G1C2+GzβGx(2G2C2+G1C1+G2C1+G3C1))+(G1G2+1β(G1G2GzGx+G2G3GzGx))=0.
The modified oscillation condition and oscillation frequency are
(17)(1+k)(G1+G2+G3)G1-2kG2=C2C1(18)ωo′=G2(G1+(kG3/(1+k)))C1C2=ωo+(k1+k)G2G3C1C2.
Equations (17) and (18) show that the parameter k slightly changes the oscillation condition and oscillation frequency, respectively. Again, this slight deviation can be overlooked because the parameter k represents a very small value on the proposed circuits. The active and passive sensitivities for this circuit are determined in (19). Equation (19) shows that the active and passive sensitivities are all low because the parameter k is nearly zero:
(19)SG2ωo′=-SC1ωo′=-SC2ωo′=12,SGzωo′=-Sβωo′=12(kG3(1+k)2G1+k(1+k)G3),SGxωo′=-12(kG3/(1+k)(1+k)G1+kG3),SG1ωo′=12(1+kk(1+G3)+1),SG3ωo′=12(kG3(1+k)G1+kG3).
The circuit depicted in Figure 4(c) has the following modified characteristic equation:
(20)S2((1+GzβGx)(C2+C3)C1)+S(GzβGx+GzβGx(G2C3+2G2C2+G1C1+G2C1))G1C1+G2C1-G1C2+GzβGx(G2C3+2G2C2+G1C1+G2C1))+(G1G2-1βG1G2GzGx)=0.
The modified oscillation condition and oscillation frequency are
(21)(1+k)(1+G2G1)+kG2C3G1C1=C2C1,(22)ωo′=(1-k)G1G2(1+k)C1(C2+C3)=1-k1+kωo.
Equations (21) and (22) show that the parameter k affects the oscillation condition and oscillation frequency, respectively. However, the influence of the nonideal effect can be nearly disregarded because the parameter k is a very small value that ideally approaches zero. The active and passive sensitivities of the circuit are
(23)SG1ωo′=SG2ωo′=-SC1ωo′=12,SGxωo′=-SGzωo′=Sβωo′=Gz1-k2,SC2ωo′=-12(C2C2+C3),SC3ωo′=-12(C3C2+C3).
Equation (23) shows that when C3>C2 is set, the values of SC2ωo′ and SC3ωo′do not exceed 50%. In addition,SGxωo′,SGzωo′, andSβωo′ approach zero because the admittance Gz is a very small value (Gz=0, in ideal case). Thus, the active and passive sensitivities are all low. Thus, to eliminate the nonideality effects and reduce the influence of sensitivity on the proposed circuits, the following conditions should be met: Gx≫Gz, Gx≫G2, and C3>C2. In considering the integration aspects, the proposed oscillator circuits with the top plate and bottom plate parasitic capacitances of C1 and C2 may render to alter the order of the oscillator circuits and change its oscillation frequency. To reduce the influences of the top plate and bottom plate parasitic capacitances of C1 and C2 on the proposed oscillators, an advanced layout technology can be applied to overcome this obstacle [31]. Table 2 summarizes the key equations for the proposed oscillators.
The frequency stability is an important performance criterion for sinusoidal oscillators [1]. The frequency stability factor SF is defined as
(24)SF=dΦ(μ)dμ|μ=1,
where μ=ω/ω0 and Φ(μ) represents the phase function of the open loop transfer function for the oscillator circuit. Using the definition expressed in (24), Table 2 gives the frequency stability factor for the proposed oscillators. This table shows that good frequency stability can be obtained by choosing a larger value of n for the proposed circuits.
4. Simulation and Experimental Results
To verify the feasibility of the proposed circuits, commercial AD844AN ICs were adopted to implement an OTRA (Figure 3) to execute the experimental tests. All experiments were performed at a supply voltage of ±5 V. The proposed circuits were also simulated with circuit simulation program HSPICE using the CMOS OTRA implementation as shown in Figure 2. Feasible design procedures of the oscillation condition and the oscillation frequency for the proposed oscillators (Figure 4) were arranged as follows. For Figure 4(a) circuit, C1=C2 was first assigned and an oscillation frequency was specified. Therefore, the values R1 and R2 can be determined using (4). For the Figure 4(b) circuit, R1=R2 and C2=nC1 were chosen. From (6) and (7), R3 can be determined when an oscillation frequency was assigned. For the final oscillator (Figure 4(c)), C2=3C1 was first assigned and thus the ratio of R1/R2 was decided from (9). Subsequently, the value of C3 can be determined from (10) when an oscillation frequency was specified. For example, the oscillator in Figure 4(a) was designed with R1=2.43 kΩ, R2=1.1 kΩ, and C1=C2=1 nF. Together with the nonideal parameters β=0.98, Rx=50Ω, and Rz=3 MΩ, this resulted in 94.98 kHz theoretical oscillation frequency. The experimental results in Figure 6(a) show an oscillation frequency of 97.54 kHz, which is close to the theoretical prediction. The percentage error between theoretical and experimental result is 2.62%. Figure 6(b) displays the corresponding frequency spectrum. The percentage total harmonic distortion (THD) was measured as 2.52%. The experimental result shows the slight distortion on this circuit because Figure 4(a) circuit suggests a compact circuit topology with minimum RC design [9, 27, 28]. However, an additional auxiliary amplitude control circuit and technology can be used to yield a lower distortion of the generated output signal through external means [32]. The oscillator of Figure 4(b) was designed with R1=R2=10.83 kΩ, R3=29.6 kΩ, and C1=0.1 nF, C2=0.2 nF together with the nonideal parameters β=0.98, Rx=50Ω, and Rz=3 MΩ. Figure 7 shows the experimental results of the output waveform and the corresponding frequency spectrum. In this case, the theoretical value of the oscillation frequency is 104.16 kHz, whereas experimental results (Figure 7(a)) reveal an oscillation frequency of 102.5 kHz. The percentage error between theoretical and experimental result is 1.59%. The percentage THD was measured as 2.64%.
Experimental results for the circuit (Figure 4(a)): (a) output waveform and (b) corresponding frequency spectrum.
Experimental results for the circuit (Figure 4(b)): (a) output waveform and (b) corresponding frequency spectrum.
The oscillator in Figure 4(c) was designed with R1=2 kΩ, R2=1 kΩ, and C1=0.1 nF, C2=0.3 nF, C3=12.4 nF. The theoretical value of the oscillation frequency was determined as 99.85 kHz. The experimental results in Figure 8(a) reveal an oscillation frequency of 101.3 kHz. The percentage error between theoretical and experimental result is 1.43%. Figure 8(b) indicates that the corresponding frequency spectrum and the percentage THD was measured as 2.98%.
Experimental results for the circuit (Figure 4(c)): (a) output waveform and (b) corresponding frequency spectrum.
Considering the achievements in CMOS technology, Figure 2 presents an alternative implementation of OTRA for simulation testing. For this purpose, all of the proposed circuits in Figure 4 were simulated using the HSPICE program based on the CMOS OTRA (Figure 2). All simulations were performed by TSMC 0.35 μm MOS transistor parameters with the same aspect ratios as those in [15]. The CMOS OTRA (Figure 2) was biased with a power supply of ±2.5 V. The bias current and voltages IB=30μA, Vg1=-1 V, and Vg2=1 V were set. Figure 9(a) shows the simulation results of the output waveform for Figure 4(a) with R1=21.3 kΩ, R2=9.85 kΩ, C1=0.1 nF, and C2=0.1 nF, where R1 was designed to be larger than R2 to achieve good frequency stability. Simulation results indicate that the oscillation frequency is 108.48 kHz (theoretical value is 109.87 kHz), yielding a percentage error of only 1.26% between the theoretical and simulation oscillation frequency results. These slight deviations in the oscillation frequency of the circuit from theoretical values were caused by the nonideality of the CMOS OTRA. Figure 9(b) shows that the simulation result of the frequency spectrum and the percentage THD was analyzed as 2.59%. The circuit in Figure 4(b) was simulated with the following values: R1=12 kΩ, R2=12 kΩ, R3=12 kΩ, C1=0.05 nF, and C2=0.16 nF. Under these design values, the theoretical value of the oscillation frequency was calculated as 148.28 kHz. Figure 10 shows the simulation results of the output waveform and its output frequency spectrum. Figure 10(a) shows that the oscillation frequency of the output waveform is 150.01 kHz. Figure 10(b) shows that the percentage THD was analyzed as 2.71%, yielding a 1.15% percentage error between theoretical and simulation result of the oscillation frequency.
Simulation results for the circuit (Figure 4(a)) using CMOS OTRA (Figure 2): (a) output waveform and (b) corresponding frequency spectrum.
Simulation results for the circuit (Figure 4(b)) using CMOS OTRA (Figure 2): (a) output waveform and (b) corresponding frequency spectrum.
For the circuit in Figure 4(c), the passive components were chosen as R1=20 kΩ, R2=9 kΩ, C1=0.05 nF, C2=0.15 nF, and C3=0.1 nF. This design yields a theoretical oscillator frequency of 106.1 kHz. Figure 11(a) shows the output waveform view obtained from HSPICE simulation for the chosen example. Simulation results show an oscillation frequency of 105.08 kHz, which is close to the theoretical prediction. The percentage error of the oscillation frequency between theoretical and simulation result is 0.96%. Figure 11(b) displays the corresponding output frequency spectrum, with the percentage THD analyzed as 0.56%. Once again, these results verify that the HSPICE simulations are in good agreement with the theoretical analysis. Simulation results show that the CMOS OTRA-based solutions provide the better output waveforms with low signal distortion. With regard to thehighest applicable operating frequency of the proposed circuit (Figure 4(c)), an experimental test with values R1=15 kΩ, R2=7.5 kΩ, C1=0.03 nF, C2=0.1 nF, and C3=0.01 nF was executed to explore this characteristic. Figure 12 shows the simulation result for the output waveform of the circuit (Figure 4(c)) with an oscillation frequency of 260.35 kHz, which is close to the theoretical value of 261.21 kHz. The highest applicable operating frequency of the proposed oscillator was only demonstrated at approximated several hundreds of kHz based on the CMOS OTRA circuit (Figure 2). In this case, the percentage error between theoretical and experimental result is 0.79%. To demonstrate the properties used to control oscillation frequency by using resistors, Figure 4(b) circuit is employed to investigate such phenomenon. By adopting C1=0.05 nF and C2=0.16 nF, R1=R2=R3=R was assigned and varied from 10 kΩ to 20 kΩ in 1 kΩ steps. Figure 13 shows the theoretical and simulation results for the variation of the oscillation frequency. The experimental results correspond with the theoretical prediction. Experimental tests suggest that the proposed oscillators can be implemented using commercially available AD844AN ICs or CMOS technology.
Simulation results for the circuit (Figure 4(c)) using CMOS OTRA (Figure 2): (a) output waveform and (b) corresponding frequency spectrum.
Simulation result of the highest applicable oscillation of the circuit (Figure 4(c)).
Variation of the oscillation frequency against R for the circuit (Figure 4(b)).
5. Conclusions
This study reports three new sinusoidal oscillators that have not been seen in the open literature. Each circuit consists of a single OTRA with a few external passive components. The first circuit features the least RC components design. The second and third circuits provide independent control of the oscillation condition and oscillation frequency, respectively. The proposed circuits also exhibit low active and passive sensitivities to oscillation frequency, and most parasitic parameters in the proposed circuits disappear due to the OTRA’s internal ground input terminals. The HSPICE simulations and experiment measurements in this study verify the effectiveness of the proposed circuits. The proposed topologies provide brand-new sinusoidal oscillators for OTRA devices. Because of their simplicity, these new schemes can be expected to find wide applications in modern analog circuit systems.
Conflict of Interests
The author declares that there is no conflict of interests regarding the publication of this paper.
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