Analysis of Random Variation in Subthreshold FGMOSFET

The analysis of random variation in the performance of Floating Gate Metal Oxide Semiconductor Field Effect Transistor (FGMOSFET) which is an often cited semiconductor based electronic device, operated in the subthreshold region defined in terms of its drain current (I D ), has been proposed in this research. I D is of interest because it is directly measurable and can be the basis for determining the others. All related manufacturing process induced device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account.The analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy. By using such result, the strategies for minimizing variation in I D can be found and the analysis of variation in the circuit level parameter of any subthreshold FGMOSFET based circuit can be performed. So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit.


Introduction
The FGMOSFET in subthreshold region has been found to be an extensively utilized semiconductor based electronic device for low voltage/low power circuits [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16].The concept of variability aware design has been applied to such low voltage/low power circuits for handling the effects of the manufacturing process induced device level random variations [6,[10][11][12][13][14][15][16].The examples of these variations are the variation in channel width () and channel length () and so forth.These device level variations affect the circuit level performances of FGMOSFET such as   , transconductance (  ), and drain to source resistance ( ds ).Similar to the ordinary Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the subthreshold FGMOSFET is more susceptible to these variations than that in the above-threshold region and   has been found to be the key circuit level performance as it is directly measurable and can be the basis for determining the others according to their relationships.
According to the importance of   , various analyses of random variation in   of the ordinary MOSFET caused by manufacturing process induced device level random variations have been performed in the analytical manner where the subthreshold region operated MOSFET has also been concerned [17][18][19][20][21][22][23].For FGMOSFET, on the other hand, the previous studies have been mostly focused on variations in the circuit level performances of certain FGMOSFET based circuits where subthreshold FGMOSFET based circuits have also been considered [6, 10-12, 15, 23-29].Unfortunately, the analysis results of these previous researches are applicable only to their dedicated circuits.Moreover, the variability analysis of a single subthreshold FGMOSFET, which is more versatile as it is applicable to any subthreshold FGMOSFET based circuits, has never been performed in any previous work.
Hence, the analysis of random variation in   (Δ  ) of subthreshold FGMOSFET caused by manufacturing process induced device level random variations has been proposed in this research.All related device level random variations, their statistical correlations, and low voltage/low power operating condition have been taken into account.The obtained analysis result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy.By using the obtained result, the strategies for minimizing Δ  can be found and the analysis  of variation in the circuit level performance of any subthreshold FGMOSFET based circuit can be done.So, the result of this research has been found to be beneficial to the variability aware design of subthreshold FGMOSFET based circuit which is an interesting low voltage/low power semiconductor application.In the next section, the overview of FGMOSFET will be addressed followed by the proposed analysis in Section 3. The verification of the analysis result and discussions will be, respectively, given in Sections 4 and 5. Finally, the conclusion will be drawn in Section 6.

The Overview of FGMOSFET
FGMOSFET is a special type of MOSFET with an additional gate, namely, floating gate isolated within the oxide.A crosssectional view of an N-type FGMOSFET with  inputs where  > 1 can be shown as in Figure 1 where the symbol and equivalent circuit are shown in Figure 2.Such equivalent circuit is composed of a MOSFET,  input capacitances ( 1 ,  2 ,  3 , . . .,   ), overlap capacitance between floating gate and drain ( fd ), overlap capacitance between floating gate and source ( fs ), and parasitic capacitance between floating gate and substrate ( fb ).
Let {} = {1, 2, 3, . . ., } and let any th input capacitance be denoted by   ; the floating gate voltage,  FG , can be given by where   is the input voltage at any th input gate,   is the drain voltage,   is the source voltage, and   is the bulk voltage.Moreover, Q stands for the charge stored on the floating gate.Finally,   denotes the total capacitance of the floating gate which can be defined as Let   ,  fd ,  fs , and  fb denote the coupling factor of any th input gate, drain, source, and bulk and be defined as   =   /  ,  fd =  fd /  ,  fs =  fs /  , and  fb =  fb /  , respectively;  FG can be alternatively given as in (3).From either (1) or (3), it can be seen that  FG depends on   ,   ,   , and   : where  denotes charge stored on the floating gate per   and is equal to Q/  .

The Proposed Analysis
By using  FG as given by (3),   of the subthreshold region operated FGMOSFET can be given without assuming that 1 ≫ exp[−  /  ] for covering the low voltage/low power operating condition which may have very low   that invalidates this assumption, as where  0 , , where variations in the physical parameters of  0 , for example, those in  ox (Δ ox ) and  th (Δ th ), have been taken into account by Δ 0 .By using (4), derivatives in (5) can be given by From ( 5)-( 6), it can be seen that Δ  is very mathematically cumbersome.So, it is worthy to look for the alternative manners of analysis, for example, the per-unit based analysis which performs the analysis in terms of the per-unit value of Δ  (Δ  /  ).By using ( 4)-( 6), Δ  /  can be given as follows: where Δ/, Δ/, Δ/, Δ/, Δ 0 / 0 , Δ fd / fd , Δ fs /  fs , Δ fb / fb , and Δ  /  are the per-unit values of Δ, Δ, Δ, Δ, Δ 0 , Δ fd , Δ fs , Δ fb , and Δ  , respectively.
Since it has been found that Δ  /  is much more compact than Δ  , the per-unit based analysis is preferable and has been chosen for this research.It has also been found that Δ 0 and Δ contribute Δ  in the similar directions which are opposite to that of Δ.Finally, the directions of contributions to Δ  of Δ, Δ fd , Δ fs , Δ fb , and Δ  depend on   ,   ,   , and   whereas that of Δ is solely dependent on the polarity of .As Δ  /  is a random variable similar to its contributors, that is, Δ, Δ, Δ, Δ, Δ 0 , Δ fd , Δ fs , Δ fb , and Δ  , it is convenient to analyze its statistical behavior by using its standard deviation as its mean is equal to zero similar to those of the contributors.By taking the statistical correlations of the contributors into account, the standard deviation of Δ  /  ( Δ  /  ) has been found to be given by where  2 Δ/ denotes the variance of Δ/ and {Δ/} = {Δ/, Δ/, Δ/, Δ/, Δ 0 / 0 , Δ fd / fd , Δ fs / fs , Δ fb /  fb , Δ  /  }.Moreover,  Δ,Δ denotes the correlation coefficient of Δ and Δ which displays the degree of their statistical correlation; for example,  Δ,Δ denotes the correlation coefficient of Δ and Δ and displays the degree of their statistical correlation.It can be seen from ( 8) that the 1st up to the 9th terms of  Δ  /  have been solely contributed by each of  2 Δ/ 's where the others have been contributed by the statistical correlations based terms.Moreover, by keeping in mind that Δ, Δ, Δ, Δ, Δ 0 Δ fd , Δ fs , Δ fb , and Δ are zero mean random variables,  Δ,Δ can be obtained by using (9) where [⋅] stands for the expectation operator:

Verification of the Analysis Result
The proposed analysis result has been verified at the nanometer level based on the 65 nm level CMOS process technology, two-input FGMOSFET of both N-type and P-type, and SPICE BSIM4 [30] with all necessary SPICE parameters provided by PTM.Since two-input FGMOSFET has been assumed, we let  = 2; that is, It should be noted that both  1 and  2 can be arbitrary constants as our device is not in the triode region which is the only region of FGMOSFET that the coupling factors are functions of   [31].So, we let  1 =  2 = 0.5 in order to balance the influence of both FGMOSFET inputs.We also let  = 120 nm and  = 80nm and also assume that   ≫  fd ,  fs ,  fb and Q is extremely small as has been done in many previous works on subthreshold FGMOSFET, for example, [1-3, 6-8, 11, 15].For making the influences of all device level variations be unbiased, all of such variations have been assumed to be statistically equivalent by letting them be normally distributed with zero means and 1% standard deviations.As a result, ΔΔ such as ΔΔ employs a normal product distribution [32] as the products of the manufacturing process induced device level random variations, for example, ΔΔ, Δ 0 Δ, and ΔΔ, are the product of two normally distributed random variables.Moreover, all  Δ,Δ 's have been assumed to be given by 0.5 which is a reasonable estimation [33].So, each device level variation must be expressed in terms of a weighted sum of its correlated and uncorrelated components which are both normally distributed [33] and have equal weights given by √ 0.5.
In order to perform the verification, the formulated  Δ  /  has been compared to its SPICE BSIM4 based reference ( Δ  /  | SPICE ) obtained by using the Monte-Carlo SPICE simulation with 1000 runs.The SPICE BSIM4 based modelling of FGMOSFET with two inputs can be done by using the two-input version of the equivalent circuit of FGMOSFET in Figure 2 where the core MOSFET has been modelled by using the SPICE BSIM4 and the simulation methodology proposed in [34] has been adopted for solving the convergence problem of the simulator.
As From Figures 3 and 4 where  Δ  /  and  Δ  /  | SPICE have been, respectively, shown in blue lines and red dots for Ntype subthreshold FGMOSFET (green lines and black dots for P-type device), highly strong agreements between  Δ  /  and  Δ  /  | SPICE can be observed.Moreover, the average errors of  Δ  /  from  Δ  /  | SPICE determined by using the data sets of Figure 3 have been found to be 1.6245% and 1.8904% for N-type and P-type subthreshold FGMOSFET based comparison.On the other hand, such errors determined by using the data sets of Figure 4 have been found to be 1.8244% and 1.9518% for the N-type and P-type device based comparison, respectively.This means that the analysis result is very accurate for both N-type and P-type subthreshold FGMOSFET.If desired,  Δ  /  can fit  Δ  /  | SPICE obtained by using the data from more advanced technology node, for example, 45 nm, 32 nm, and 28 nm.For doing so, the optimum parameters of subthreshold MOSFET's   such as  0 , , , and , extracted from the measured   of the advanced technology node under consideration by using the optimization algorithm [35], must be adopted.From Figures 3 and 4, it can be seen that  Δ  /  of the subthreshold FGMOSFET of both N-type and P-type grow larger when either | 1 | or | 2 | are lowered.This implies that the subthreshold FGMOSFET under very low voltage/low power operating condition is subjected to very large Δ  .It can also be seen that both  Δ  /  's with respect to | 1 | and | 2 | of the P-type subthreshold FGMOSFET are lower than those of the N-type device.This means that the P-type device is more robust to the manufacturing process induced device level random variations than its N-type counterpart and has been found to be more preferable.Finally, even though the aforementioned average errors of the P-type device are larger than those of the N-type counterpart, it does not mean that our analysis result is more suitable to the less robust device.This is because the differences in these average errors which are very small as they are less than 0.3% are caused by the differences between the extraction errors of the subthreshold MOSFET's drain current analytical model parameters from the 65 nm level CMOS technology based drain current data of the N-type and P-type MOSFET.
Apart from yielding the above strategies, our Δ  /  is also applicable to the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit in which the formulated  Δ  /  given by (8) has been found to be beneficial as well.For performing such analysis, we let the circuit level performance of the subthreshold FGMOSFET based circuit of our interest be ; thus, the random variation in  (Δ) can be given by where ,   , and Δ  /  denote number of FGMOSFETs within the circuit which contribute ,   , and Δ  /  of any th FGMOSFET which can be determined by using (7), respectively.It can be seen from ( 19) that Δ can be determined after every Δ  /  has been found.According to the definition of Δ  /  above, it is a zero mean random variable and so does Δ.As a result, it is convenient to analyze the statistical behavior of Δ by using its standard deviation, that is,  Δ .By taking the statistical correlations between each random variation in   into account,  Δ can be given by (20), where  Δ  ,Δ  denotes the correlation coefficient of Δ  and Δ  which are the random variations in   and   , that is,   of any th FGMOSFET where  ̸ = , respectively.Since  Δ  /  and  Δ  /  are, respectively,  Δ  /  of th and th FGMOSFET, they can be determined by using (8).After finding all  Δ  /  's and  Δ  /  's,  Δ can be obtained: As a practical example, let  be the output current ( out ) of the subthreshold FGMOSFET based OTA [11] whose core circuit has been depicted in Figure 5 where  + ( − ) and   denote the voltage at the positive (negative) input of the OTA and the supply voltage, respectively.For this OTA,  1 and  2 which have two inputs serve as an input differential pair and the averaging circuit has been included for improving the linearity.According to [11],  out can be given in terms of   of  1 and  2 , that is,  1 and  2 as Since the bodies of these FGMOSFETS are grounded and their sources are tied together as shown in Figure 5, we have  1 =  2 = 0 and  1 =  2 .Thus, we can let both  1 and  2 be given by   .As a result,  1 and  2 can be, respectively, given by where  11 ( 21 ),  So, the random variation in  out (Δ out ) can be given by using (19) with  = 2 as M 3 Averaging circuit Figure 5: The core circuit of the subthreshold FGMOSFET based OTA proposed in [11].
where both Δ 1 / 1 and Δ 2 / 2 can be determined by using (7) as they are Δ  /  of  Moreover, the standard deviation of Δ out ( Δ out ) can be obtained by using (20) with  = 2 as follows: where  Δ 1 / 1 and  Δ 2 / 2 can be determined by using (8) 6 where  Δ out has been expressed in a perunit basis with respect to the nominal  out and the magnitude of  Δ 1 ,Δ 2 has been assumed to be 0.5 which implies a reasonable medium degree of correlation between Δ 1 and Δ 2 .From Figure 6, it can be seen that  Δ out is increased with respect to  Δ 1 / 1 and  Δ 2 / 2 .It can also be seen that even small amounts  Δ 1 / 1 and  Δ 2 / 2 can induce considerably large  Δ out .As an example,  Δ 1 / 1 = 0.09 and  Δ 2 / 2 = 0.08, that is, Δ 1 and Δ 2 of 9% and 8% of the nominal I 1 and I 2 , respectively, yield  Δ out = 0.26 which is equivalent to Δ out as large as 26% of the nominal  out .So, it can be seen that the adverse effect of Δ  to the performance of subthreshold FGMOSFET based circuits is significant.

Conclusion
In this research, the analysis of Δ  of subthreshold FGMOS-FET, which is an often cited semiconductor based electronic device, has been performed.All related device level random variations, that is, Δ, Δ, Δ, Δ, and Δ 0 which cover variations in the physical parameters of  0 , for example, Δ ox and Δ th , Δ  , Δ fd , Δ fs , and Δ fb and their statistical correlations, have been taken into account.Moreover, the low voltage/low power operating condition has also been concerned.The obtained result has been found to be very accurate since it can fit the nanometer level SPICE BSIM4 based reference with very high accuracy where the average error of each verification scenario has been, respectively, found to be 1.6245% (1.8904%) and 1.8244% (1.9518%) for Ntype (P-type) subthreshold FGMOSFET.
Based on the proposed analysis result, it has been found that the subthreshold FGMOSFET under low voltage/low power operating condition is subjected to large Δ  and the P-type subthreshold FGMOSFET has been found to be a more preferable device as it is more robust to the manufacturing process induced device level random variations than its N-type counterpart.It has also been found that Δ  can be minimized by minimizing ,  fd ,  fs , and  fb , maximizing , and avoiding the extremely low voltage/low power operating condition.The design technics for obtaining minimum ,  fd ,  fs , and  fb and maximum  have been suggested.Moreover, the analysis of variation in the circuit level performance of any subthreshold FGMOSFET based circuit can be done based on the proposed result as illustrated above in which the subthreshold FGMOSFET based OTA has been focused on.So, the result of this research has been found to be beneficial to the variability aware analysis and design of subthreshold FGMOSFET based circuit which is an interesting semiconductor application.

Figure 2 :
Figure 2: The symbol (a) and equivalent circuit model (b) of an N-type,  inputs FGMOSFET.
the resulting verification,  Δ  /  and  Δ  /  | SPICE have been comparatively plotted against the magnitude of the voltage of the 1st and 2nd input of FGMOSFET denoted by | 1 | and | 2 |, respectively.The minimum values of both | 1 | and | 2 | are 0 volts and the maximum values have been chosen so that the both N-type and P-type FGMOSFETs operate in the subthreshold region.The comparative plots of  Δ  /  and  Δ  /  | SPICE against | 1 | (where | 2 | = 0) of Ntype and P-type subthreshold FGMOSFET can be shown in Figure 3 where the similar plots against | 2 | (where | 1 | = 0) are shown in Figure 4.