Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO2 and Si3N4/SiO2 Gate Dielectrics

The total ionizing dose irradiation effects are investigated in Si vertical diffusedMOSFETs (VDMOSs) with different gate dielectrics including single SiO 2 layer and double Si 3 N 4 /SiO 2 layer. Radiation-induced holes trapping is greater for single SiO 2 layer than for double Si 3 N 4 /SiO 2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO 2 at lower oxidation temperature. Gate bias during irradiation leads to different VTH shift for different gate dielectrics. Single SiO 2 layer shows the worst negative VTH at VG = 0V, while double Si3N4/SiO2 shows negative VTH shift at VG = −5V, positive VTH shift at VG = 10V, and negligible VTH shift at VG = 0V.


Introduction
Silicon power MOSFET, especially vertical diffused MOSFET (VDMOS), is widely used for high power application due to its mature technology and cost efficiency. Nowadays, VDMOS is often used under harsh environment such as space, where it suffers from cosmic radiation [1][2][3][4]. To operate normally in space environment, Si VDMOSs must be able to withstand ionizing radiation such as total ionizing dose (TID). In this paper, we investigate TID effects in Si VDMOS with different gate dielectrics including single SiO 2 layer and double Si 3 N 4 /SiO 2 layer, different oxidation temperatures of SiO 2 , and different gate bias during irradiation.

Experiment Set-Up
The Si VDMOSs considered here are devices with wellknown standard fabrication process except the gate dielectric deposition condition. Different silicon dioxide deposition conditions are carried out including different oxidation temperature from 800 ∘ C to 1000 ∘ C and with and without postoxidation annealing. In particular, double gate dielectric layer Si 3 N 4 /SiO 2 , having the same total thickness 50 nm (20 nm/30 nm) as that of single SiO 2 layer, is fabricated to evaluate its hardness towards TID.
The irradiation test is performed with unpackaged devices wire-bonded on the test board under Co 60 gamma source at a dose rate of 50 rad (Si)/s at room temperature, and the devices are remeasured after a total dose of 100 Krad is reached after 33 minutes. Irradiation was performed with different gate voltages ( ) of 10 V, 0 V, and −5 V, with source terminal grounded and drain terminal of small voltage to guarantee a small current of about 100 mA for = 10 V and drain terminal of 200 V (rated breakdown voltage). The bias-stress-only test is also performed without irradiation to account for the electrical stress influence, such as TH , . The bias-stress test is carried out by using the same biases ( of 10 V, 0 V, and −5 V) and time (33 minutes) comparable to those used in the irradiation experiments. Current-voltage characteristics are measured using Agilent 2902A parameter analyzer, and the measurements are carried out before and right after the irradiation/bias-stress. before and after TID irradiation with = 10V during irradiation. Two types of gate dielectrics with the same total thickness of 50 nm are investigated including normal SiO 2 layer (Figure 1(a)) and double Si 3 N 4 /SiO 2 layer (Figure 1(b)), which is claimed to be more TID tolerant [5][6][7][8][9]. It can be observed that the threshold voltage TH shifts negatively for single SiO 2 layer indicating a net holes' trapping during positive-bias irradiation, and Δ TH increases from 0.2 V to 0.71 with rising oxidation temperature from 800 ∘ C to 1000 ∘ C. The high temperature annealing (HTA) step after oxidation adds to the negative shift, suggesting a higher hole trapping ability. However, for double Si 3 N 4 /SiO 2 layer, TH shifts positively at = 10V with a smaller Δ TH = 0.14 V than that of SiO 2 . It can be explained that, at positive-bias irradiation with = 10 V, as shown in Figure 5(a), the irradiation created electrons in the SiO 2 layer are swept to the Si 3 N 4 and trapped there, forming net electrons trapping by compensating with the irradiation created holes in Si 3 N 4 [10][11][12]. The number of electrons trapped in the Si 3 N 4 is higher than the holes trapped in the SiO 2 , resulting in a net positive TH shift. Figure 2 shows versus characteristics of Si VDMOS with different gate dielectrics and different oxidation conditions before and after TID irradiation with = 10V during irradiation. It can be observed that the devices with both single SiO 2 dielectrics and double Si 3 N 4 /SiO 2 dielectric (Figures 2(a) and 2(b)) have about the same value both before and after a total dose of 100 Krad (Si), indicating excellent gate control. The device with double Si 3 N 4 /SiO 2 dielectric (Figure 2(b)) shows higher of 1.6 S compared to that of single SiO 2 layer (1.3∼1.4 S) at = 1 V, which is due to a higher effective gate capacitance. The capacitance of Si 3 N 4 /SiO 2 gate dielectric is measured to have a gate capacitance of 1.6 × 10 −9 F, while SiO 2 gate dielectric has a gate capacitance of 1.1 × 10 −9 F due to a higher dielectric constant of Si 3 N 4 with the same total thickness.

Results and Discussion
To exclude the electrical stress response from the bias irradiation test, the bias-induced degradation was separately After TID measured at biases and times compared to those used during irradiation. The results show that the electrical stress has trivial influence (<5%) on TH compared with the TID bias irradiation effects. Figure 3(a) shows Δ TH of different gate dielectrics at different gate biases during irradiation including = −5 V, = 0 V, and = 10 V. It can be observed that, for single gate dielectric SiO 2 with different oxidation conditions, TH shifts all negatively, and the SiO 2 layer fabricated at lower temperature presents a smaller TH shift at all gate biases during irradiation. It can also be observed that the threshold voltage TH shifts the most at irradiation bias of = 0 V for single SiO 2 gate dielectric. It can be explained that, at = 0 V, the irradiation created holes are freely dangling around in SiO 2 , which are more easily trapped in the SiO 2 , forming positive trapped charges, leading to negative TH shift. For irradiation bias of = −5V, there are similar chances that irradiation created holes can be trapped in the SiO 2 , while, simultaneously, irradiation created electrons are swept to the SiO 2 /semiconductor interface, forming more interface defects than in the case of irradiation bias of = 0 V, which can be confirmed by calculating, respectively, the ot and it values by subthreshold midgap technique (SMGT) [12,13], as is shown in Figure 3(b).
In an ideal device, the drain current and gate voltage are related by ∼ exp( ) in subthreshold regime. When plotted as log( ) versus , the straight -characteristic can be extrapolated to a calculated midgap current. Comparing the preirradiation and postirradiation characteristics, the midgap voltage shift, Δ mg , as well as the change in subthreshold swing (inverse slope), Δ , can be determined. The value of Δ mg is equivalent to Δ ot and Δ is proportional to Δ it . The subthreshold charge separation technique has proven to be the easiest to perform and is the most widely used. The value of Δ ot is obtained from Δ mg assuming the following relation: where ox = ox ox .
(2) The difference between the pre-and postirradiation subthreshold swings, Δ , is calculated by the following relations: where it stands for the interface trap induced capacitance, is the Boltzmann constant, is the temperature, and the Fermi potential 0 can be calculated as follows: Figure 3(b) shows Δ ot and Δ it calculated by SMGT method using (1) to (4) of both single gate dielectric SiO 2 and double gate dielectric Si 3 N 4 /SiO 2 at different gate bias including = −5 V, = 0 V, and = 10 V. It can be observed that, for single SiO 2 dielectric, ot are similar in both = −5 V and = 0 V, while it is larger in = −5 V than in = 0 V, resulting in a compensation of TH effects. The TH shifts negatively at all bias irradiation cases for single SiO 2 gate dielectric layer; for double gate dielectric Si 3 N 4 /SiO 2 , however, TH shifts negatively in = −5 V, and TH shifts positively in = 10 V and barely shifts in = 0 V. By calculating ot and it , respectively, it can be observed that, at = −5 V, more holes are swept towards/to the Si 3 N 4 layer, where they can be more easily trapped compared to SiO 2 [5]. For = 10 V, irradiation created electrons are trapped in Si 3 N 4 , forming negative trapped charges, leading to positive TH shift.
Under bias irradiation, electron/hole pairs are being generated in a MOSFET. At = 0 V, electrons/holes get more chances to recombine at first, forming less trapped holes and interface defects. At = −5V or = 10V, less electrons/holes recombine at higher electric field, leading to more trapped holes and interface defects, as illustrated in Figure 4. For single gate dielectric SiO 2 , the oxide trapped charges ot increase with the absolute electric field | |, with the least oxide trapped charges at = 0 V due to recombination of more holes/electrons at the beginning. For double gate dielectric Si 3 N 4 /SiO 2 , there are more net oxide trapped charges at = −5 V than at = 10 V, which can be explained as follows.
Under positive-bias irradiation, the charges in the SiO 2 are mostly due to holes trapping at the oxide/silicon interface. In contrast to this, the negative charges due to the electrons from the oxide layer and the positive charges due to the holes from the nitride compete to determine both the magnitude and the sign of the charges in the Si 3 N 4 , as illustrated in Figure 5(a). The electrons generated in the oxide layer are swept to the nitride layer easily because no electron barrier exists at the Si 3 N 4 /SiO 2 interface. The total number of holes generated in the oxide and escaping initial recombination is assumed to be approximately proportional to the oxide thickness, which is consistent with what is observed in Figure 4(a) with more ot in single SiO 2 layer than in double Si 3 N 4 /SiO 2 layer at = 10 V. For negative bias irradiation, Si 3 N 4 /SiO 2 shows negative TH shift, larger in magnitude than that for positive-bias irradiation. This occurs because the nitride/oxide interface has more trapped holes than trapped electrons due to the holes moving from the SiO 2 without hole barrier at the interface, as illustrated in Figure 5(b). Also, some of the holes generated in the oxide are trapped in the oxide. Due to the net trapping of holes in both the oxide and nitride, there is addition of charges for the negative bias case [10][11][12][13].

Conclusions
The gate dielectric effects and gate bias dependence of TID effects on Si VDMOS have been evaluated. Single gate dielectric SiO 2 presents negative TH shift at either positive or negative gate bias, which improves with lower oxidation temperature. Double gate dielectric Si 3 N 4 /SiO 2 shows negative TH shift at negative gate bias due to net holes trapping in Si 3 N 4 /SiO 2 and positive TH shift at positive gate bias due to net electron trapping.
These results provide insight into the mechanisms and magnitude of the TID responses of Si VDMOS with SiO 2 and Si 3 N 4 /SiO 2 gate insulators, and Si 3 N 4 /SiO 2 is proved to be more TID tolerant.