Investigation and Analysis of the Simultaneous Switching Noise in Power Distribution Network with Multi-Power Supplies of High Speed CMOS Circuits

The paper studies a simultaneous switching noise (SSN) in a power distribution network (PDN) with dual supply voltages and two cores.This is achieved by reducing the admittancematrixY of the PDN then calculating frequency domain impedance with rational function approximation using vector fitting.This paper presents a method of computing the simultaneous switching noise through a switching current, whose properties and details are described.Thus, the results are discussed and performed usingMATLAB and PSpice tools. It demonstrated that the presence of many cores in the same PCB influences the SSN due to electromagnetic coupling.


Introduction
At present, there is an ever-greater integration in electronic circuits resulting from grouping in the same card the complex chips with different natures [1].These electronic circuits are submitted to important electromagnetic disturbances.The majority of these disturbances is the result of the miniaturization of the components, the increase in the performances, increasing the frequency, and decreasing the supply voltages.Therefore, it becomes necessary to take into account these disturbances to predict the behavior of integrated circuits.
The current and voltage of the power source are generally cumbersome.Indeed, they often cannot be directly connected to the transistors presented within the integrated circuits.Thus, the currents will have cross interconnections, the power plans, and the bondings wires before supplying the transistors.All these elements have resistance, pure inductance, and possibly a capacitance.The currents, crossing these elements, will create voltage fluctuations on arrival.This phenomenon is called simultaneous switching noise (SSN).The SSN is due to mutual inductive coupling and interconnections of power delivery networks (PDNs).So, to analyze the SSN, it is necessary to model the behavior of these inductive coupling and interconnections at high frequencies.
In relation to the topic, several papers have discussed the issue of modeling PDNs.Therefore, there are different modeling methods, such as a finite difference time domain (FDTD) method [2], transmission line method [3,4], and the transmission matrix method.The transmission line method, in particular, uses transmission line with two-dimensional array or distributed RLCG elements in SPICE, in addition to the cavity resonator process simulated in SPICE tool [5,6].Yet it is essential to mention that the transmission matrix method is based on a modeling cascade of elementary cell circuits RLCG in the package and board [7] which is more effective for analyzing PDNs.
One of the most important criteria in the design of PDNs is to ensure safe energy to the circuits when a sudden power occurs.Indeed, the elimination of SSN in multilayer PCB is a critical task in the phase of the design to assure signal integrity.Several methods have been used to reduce the harmful effects of noise transmission, such as integrated capacitors, which are used at high frequencies because of their low inductance [8,9].Another method to remove noise is the introduction of lossy components serving for the elimination of resonance based on the increase of the component loss [10].Power islands are also used in the reduction of noise by isolating the components making noise on the power bus from sensitive devices [11].
In [12], there is a new method to model the simultaneous switching noise (SSN) for systems with a single integrated circuit.This method uses the rational function of the PDN impedance in the time domain based on measurements.Our work consists also of compute the SSN but for one system with two integrated circuits or cores.Since the objective is to analyze the coupling effects between them, our method uses firstly the rational function of the PDN impedance and then the principle of vector fitting (VF) to compute its parameters and finally the reduction of the PDN admittance matrix .
After the introduction, the second section presents the analysis of the approximation with a rational function.The third deals with a method of vector fitting.The fourth consists in the applications that analyze the effect of the presence of two cores.Finally, conclusions are drawn in the last part.

PDN Impedance Function in Time Domain
In general, the power distribution network (PDN) contains many networks of capacitors with several types and different values which allow obtaining the target impedance on the required frequency range of a PCB ground and power plans.So, the design of the PDN interconnections should carry its impedance () below the target impedance at high frequency [13].In frequency domain, the example of PDN impedance as seen by the pads on the chip is illustrated by Figure 1.
The main objective in the design of the power distribution network is to provide the sufficient current for each transistor of the integrated circuit by ensuring that the power supply noise does not exceed the specified margin.Then, the target impedance  target can be defined as In frequency domain, we can write where (i)  PDN is the impedance of the PDN, (ii)  load is the transient current, and (iii)  noise is the voltage noise in the PDN.
The SSN waveform cannot be calculated directly with  PDN () because of the impedance function that cannot be extracted directly from the circuit model that contains power/ground planes and capacitors in time domain.Indeed, an impedance approximation with a rational function is necessary [12].
The impedance rational approximation in the frequency domain can be written [14] as In (3),  represents the Laplace variable,   are the poles, and   are the residues, all of them can be either real or complex conjugate pairs.The term  is a real constant and  is the order of the approximation.Let us consider a weighting function () defined as where   represent the poles of the function () and   are the residues corresponding to   .By multiplying (4) with  PDN () we import its rational approximation and we find We note that () has the same poles of (() ⋅  PDN ()). PDN () rational function approximation can be easily obtained from (5).So, we find where Equation (6) shows that the poles of  PDN () become the zeros of  fit ().We observe that the starting poles are canceled in the process of division because the poles of ( PDN ) fit () are the same of  fit ().In fact, it is enough to calculate the zeros of  fit () to obtain a good set of poles of  PDN () [14].
The calculation of the poles and the residues of the impedance rational approximation in the frequency domain can be achieved by the principle of vector fitting in two steps based on the starting poles.The first step involves the identification of the poles based on (5) which can be eventually written in this form: Equation ( 8) can also be written for  frequency points as a linear problem: where The vector fitting examined the problem of ( 8) by solving the problem of (9) using the least squares method and then passes to the calculation of the zeros by computing the eigenvalues of the matrix : where [] is a diagonal matrix containing the starting poles, and {} is a column vector of ones, and {}  is a row-vector containing the residues of ().
The second phase of vector fitting consists of calculating the residues of  PDN () directly from (6).
The rational approximation with the vector fitting in frequency domain should respect several criteria such as passivity, causality, and stability.The passivity is satisfied when the eigenvalues of Re{ PDN ()} are strictly positive [15].This leads to the optimization stage: With The first part of ( 12) minimizes the variation in the impedance matrix elements, whereas the second imposes the criterion of passivity on the disturbed model [15].The stability can be satisfied by controlling the rational approximation poles.The stability condition is, thus, equivalent to granting that the poles lie in the left-hand plane.Finally, the causality is satisfied when we reach Re(  ) < 0 [16].
After having respected these three criteria,  PDN () can be written in the frequency domain as where the  poles (  −   ,   +   ) and their corresponding residues (  −  ,   +  ) are complex conjugate pairs, and the  poles   and its corresponding residues   are real.By performing the inverse Laplace transformation, the impedance in the time domain has the following form: where () is the Dirac impulsion, ℎ() is the unit step function, and  =  cos(  /√ 2  +  2  ).It is clear that the impedance function in the time domain can be easily obtained from the rational approximation in the frequency domain.

Simultaneous Switching Noise in Power Distribution Network
Once the impedance function in the time domain is determined from (2), the SSN waveform can be calculated as follows: where * denotes the convolution operation.
For digital signals at GHz, the pulse width of switching current is in the order of 0.1 ns, and the resonance period exceeds 1 ns for typical PDNs [12].Thus, the current impulse can be seen like one with limited amplitude if the PDN  resonance period is very large compared to the impulse width of the current.
We assume that the switching current is a triangular periodic signal as indicated in Figure 2. The surface of the current impulse can be estimated by  =  0 ((  +   )/2); therefore it can be replaced by () = ().The noise is periodic and it is given by the following formula: In real circuit system, the PDN is a multiport system as represented in Figure 3.
So, the SSN of the th port is calculated by where   () is the switching current of the th port and   () is the inverse Laplace transformation of   () which represents the impedance between the th port and the th port and   () is the self-impedance of the th port and  is the number of the ports.

Computational Example: The SSN of Power Distribution Network with Dual Supply Voltages
Multiple power supply voltages are often used in modern high performance ICs, like microprocessors, to decrease power consumption without affecting circuit speed.To maintain the power distribution network impedance below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy as illustrated in Figure 4 [17].
In this section, a study of a system with two integrated circuits or cores in the same chip is presented.It comprised two equivalent circuits, one without the ground parasitic circuit return (Figure 5) and another with it (Figure 10).Our goal is to obtain the SSN through a detailed circuit analysis.

Analysis of the SSN for PDN Circuit without Ground Parasitic Circuit Return.
A lumped circuit model of a PDN as depicted in Figure 5 is considered [18].The package pins, PCB, and VRM are modeled using RL circuits.The parameters of decoupling capacitors to provide power to ICs and the noise parameters of the pins are shown by Figure 5.The integrated circuits activity is modeled by current sources.Each current source has a triangular form with an amplitude of 1 A, an impulse width of 0.2 ns, and a period of 2 ns.So, the bandwidth impedance is 3.5 GHz.The coupling between these circuits is modeled by series RLC circuits.
As already mentioned in the introduction, the model of a PCB can be extracted using different methods, such as FDTD and transmission matrix method.
The PDN is composed of several networks of decoupling capacitor, because no single decoupling capacitor network will provide a low enough inductance.Therefore, the real solution to the high-frequency decoupling problem lies in the use of multiple decoupling capacitors.The number of these capacitors and their type, values, and placement with respect to the IC are important in determining their effectiveness.Many approaches have been proposed such as the use of multiples capacitors all of the same value, the use of multiple capacitors of two different values, and the use of multiple capacitors of many different values, usually spaced a decade apart.
As already said in Section 2, to be an effective decoupling network, the impedance of the network must be kept below some target value over the range of interest.This impedance is required to compute the number of capacitors to be used in PDN, while being based on equation mentioned in [19].After computing the number  of the capacitors, it is possible to calculate the value of the total capacitor from the value of the target impedance.Finding this value and dividing it by the number  allows finding the minimum value to be used for each capacitor network.And using one of the approaches cited earlier, the model to study can be built.
The values of all resistive, capacitive, and inductive elements of the circuit have been taken from the paper [12].According to this paper, for system with a single core, these values represent a real PCB with dimensions of 80 mm ×  100 mm.This PCB contains 8 global decoupling capacitors and 4 local capacitors.In our study, we need a PCB with dimensions of 160 mm × 100 mm.This PCB must contain 16 global decoupling capacitors and 8 local capacitors and must be divided into two parts by removing 100 m of the copper constituting the upper surface of the circuit.This 100 m presents the coupling between the two parts of PCB.
The circuit rational function parameters are calculated by the principle of vector fitting.But before this calculation, it is necessary to compute the values of this function in specific range of frequency.Obtaining these values is performed by the reduction method in which all elements of the matrix  are found first, and then the reduction is applied in accordance with the principle explained below.
The circuit of Figure 5 is composed of 8 nodes where the nodes connected to the current sources are considered like two terminals.
So, the circuit admittance matrix () in the frequency domain has a size 8 × 8 whose elements are calculated as follows [20]: (i) The   elements present the admittance of the branch between node  and node  with a negative sign.
(ii) The   elements present the sum of the admittance of all branches connected to the node .
The matrix () is reduced in accordance with the two terminals 1 and 2. To do this, we write the matrix () in the form of four submatrices as shown in where "" denotes the nodes 1-2-3-4 and "" denotes the nodes 5-6-7-8, and   and   are square matrices.Since the current injection to nodes 5-6-7-8 is zero, we have   = 0, so we can extract V  according to V  from the second row in (19): Inserting (20) into the first row of (19) gives The matrix  red obtained has a size 4 × 4, but as we said previously we want to keep just the nodes of the terminals 1 and 2, so the matrix  red needs another reduction to obtain a new matrix of size 2 × 2. To find this matrix we follow the same procedure mentioned above, where we still decompose once  red into 4 submatrices   ,   ,   , and   , where "" denotes nodes 1-2 and "" denotes nodes 3-4, and   and   are square matrices.
After obtaining the reduced admittance matrix, the impedance matrix seen from terminals 1 and 2 is calculated by its inverse.Thus, the noise of the two ports is given by Figure 6 shows SSN methodology followed in this paper.
To make a comparison between the programmed theoretical calculation (VFM + reduction matrix ) and numerical computation (real circuit), the simulations of this application are made using PSpice and MATLAB tools.During the simulations, there are two factors that influence noise.The first factor accounts for the activity of the second integrated circuit ( 2 = 1 A or  2 = 0 A), and the second factor is the influence of the coupling capacitor values between the two circuits (test of several values: Figures 7 and 8).
The comparison between the results given by our method and PSpice shows first that the vector fitting is very powerful in the calculation of the poles and residues of the rational function that approximates SSN, which is illustrated by the coincidence of the two curves.The results, also, show that the presence of a second active integrated circuit increases the rate of the SSN to core 1, that is shown in Figure 7, which shows that with  2 = 1 A and the fluctuations are equal to 22 mV, while with  2 = 0 A, they are equal to 12 mV.
Presently, by changing the value of coupling capacitance chip  c12 through 1 nF instead of 100 nF, we observe that the form of the SSN in the two cores in the case of  2 = 1 A does not change.But, there are fluctuations in the second case when  2 = 0 A increase in the first port, whereas they decrease in the second port as illustrated by Figure 9.
From the results of this section we can conclude that the presence of several integrated circuits in the same chip can increase the fluctuations of the simultaneous switching noise due to the existence of coupling between these circuits.

Analysis of the SSN for PDN Circuit with Ground Parasitic
Circuit Return.This second application is for studying and calculating the simultaneous switching noise of the same PDN circuit (Figure 5) except that this time the circuit includes a ground parasitic circuit return (Figure 10), while containing the same component values with the two current sources.A reduction is made for the  matrix through the previously presented method.The number of reductions done is always equal to two, except that the size of the last reduced matrix is 4 × 4. The simultaneous switching noise in this case is calculated by where V  and V  are calculated by (18).The principle of the rational approximation with vector fitting is always used.The frequency domain noise obtained by PSpice tool is shown in Figure 11.The figure gives the noise for different values of the capacitance  c12 near of the two cores.
The study was performed again through the study of the effect of the current of the second core and the values of the coupling capacitors between the two cores.
The presence or the absence of the current of the second core has no effect on the SSN at core 1, whereas at the second core while current  2 is zero, the degree of fluctuation is presented around 1.2 V.This is justified by the presence of the coupling between the two cores.But the fluctuations in the case of  2 = 1 A are bigger than the fluctuations in the case of  2 = 0 A. The simulations of these results are shown in Figure 12.
To study the effect of the coupling capacitance between the PDNs, we keep  2 = 0 A in all simulations that follow and each time we change the capacitance values.For the electrical coupling presented by the capacitance  c12 , an increase in its values of 1 nF (Figure 12(b)) to 100 nF increases (Figure 13) the fluctuations of the SSN around 1.2 V to almost 5 mV for  c12 = 100 nF and 2 mV for  c12 = 1 nF at the second core, while this increase does not have a great influence on the SSN at the first core.Figure 13 illustrates these results.
From these results, we can conclude that the addition of ground parasitic circuit influences the form of the SSN precisely at the second core and the fluctuations become more important.We can also conclude that the larger the coupling is beside the two cores, the more important the noise is.

Conclusions
In this paper, a study is made to analyze the simultaneous switching noise in power distribution network with dual supply and two cores.Unlike Ding and Li [12], this study is initiated by the calculation of noise in the time domain by an approximation of the impedance in the frequency domain with a rational function by vector fitting and reduction matrix techniques.Then, the SSN is calculated based on switching current.The results show that the presence of multiple cores in a single card influences the SSN by increasing their fluctuations due to electrical coupling between them.It has  been also found that even if a core is not active, a noise exists at its terminals that can disrupt normal operation.According to the latest results, it is found that, the ground parasitic circuit return influences the shape of the SSN.The greater the coupling is beside the cores, the more important the noise is.

Figure 5 :
Figure 5: Lumped circuit of the PDN with dual supply voltages and two cores without circuit return.