DRV Evaluation of 6T SRAM Cell Using Efficient Optimization Techniques

. An optimization based method which uses bisection search algorithm has been proposed to evaluate the accurate value of Data Retention Voltage (DRV) of a 6T Static Random Access Memory (SRAM) cell using 45nm technology in the presence of process parameter variations. Further, we incorporate an Artificial Neural Network (ANN) block in our proposed methodology to optimize the simulation run time. The highest values obtained from these two methods are declared as the DRV. We noted an increase in DRV with temperature ( 𝑇 ) and process variations (PVs). The main advantage of the proposed technique is to reduce the DRV evaluation time and for our case, we observe improvement in evaluation time of DRV by ≈ 46 , ≈ 27 , and ≈ 8 times at 25 ∘ C for 3 𝜎 , 4 𝜎 , and 5 𝜎 variations, respectively, using ANN block to without using ANN block.


Introduction
Memory structures are now present not just as stand-alone memory chips but also an integral part of complex VLSI systems [1].SRAM plays a major role in random access memory design, but its leakage currents reduction has become a major concern in past decade.Various architectures of SRAM cell have been also proposed in this regard [2,3].The most straightforward and easier approach for reducing the leakage power is to reduce the supply voltage (  ) of the SRAM cell.Moreover, reducing it below a certain limit may result in the detrition of the stored data due to T and PVs.In SRAM cell, the critical   above which a data-bit is retained reliably is called the DRV of the cell.Figure 1 shows the reduction of leakage current with the   .Hence, operating the SRAM cell with the voltage higher than its DRV helps in reducing leakage current in standby mode [4].However, some of the circuit mismatches result in the variation of the   of transistors, which causes shifts in the DRV value.Hence, accurate estimation of DRV is a major challenge in low power SRAM design [5,6].Qin et al. developed an analytical model for DRV to get a substantial reduction in leakage current by suppressing the   to DRV [7].The most straightforward method being used to obtain the DRV is by running Monte-Carlo (MC) simulations until a desired failure probability level is reached [8].However, this method has many disadvantages.
Since obtaining the failure point is a rare event which makes MC simulation time-consuming [9].Another issue is the time to find a large number of samples to get the accurate value of the tail of the DRV distribution as shown in Figure 2(a).Importance sampling (mixture importance and sequential importance) methods are developed to improve the speed of simulation.These methods have been proved to be more effective than MC samples in obtaining the failure point [10][11][12].Wang et al. proposed two methods to evaluate DRV [13].In the first method, they propose a statistical model for DRV evaluation which uses the relationship between DRV and SNM.Mean and variance of the SNM distribution have been obtained using MC simulations, and DRV is evaluated as the value of the   at which SNM reaches zero.In the second method, a generic tail model from recursive statistical blockage has been proposed.Postfabrication methods are also developed which uses canary replica cells [14,15] and builtin self-test [16,17] to obtain DRV.However, the optimization based method proposed by G. Huang et al. [18] has been claimed to be the fastest evaluation method to obtain DRV.He formulated DRV as a time domain worst performance bound problem and then multistart point (MSP) optimization strategy is developed to evaluate the failure bound.
We use MATLAB tool (version 2015b) to evaluate DRV using optimization based method.A MATLAB code is written for the node voltage equations (Q, Q B ) of MOSFET operating in the subthreshold region [19,20].Further, we use bisection search algorithm [21] to search the optimum   , and SNM is evaluated using rotation algorithm [22].PVs are incorporated by generating 5000 quasirandom samples for the Gaussian distribution of   .To reduce the time taken for evaluation, an ANN block is incorporated which predicts the value of SNM for a particular sample point.A set of DRV values are evaluated, and the corresponding histogram is plotted.The highest value of DRV obtained or the tail point of the histogram is considered as the DRV.The procedure used by us has not been claimed so far as per our knowledge.A basic 6T SRAM cell consists of two cross-coupled inverters and two access transistors (M5 and M6) are shown in Figure 2(b).M1 and M3 PMOS transistors are pull-up transistors while M2 and M4 NMOS transistors are known as pull-down transistors.During read or write operation word line (WL) is raised high (transistors M5 and M6 become on) while in hold mode (or retention mode) WL is made low (transistors M5 and M6 turn off) and SRAM store the data present in Q and QB nodes.The ability of the SRAM cell to hold the data in retention mode is determined by the SNM of the SRAM cell.The value of SNM is determined from the butterfly curve of the cell in hold mode.Butterfly curve is a plot of voltages (Q versus QB and QB versus Q), where Q and QB are the node voltages of SRAM cell as shown in Figure 3(a).SNM is evaluated as the length of the diagonal of the maximum square that can be incorporated in the butterfly curve.Figure 3

Proposed Method
The block diagram used for DRV evaluation has been shown in Figure 4 with different colors.The evaluation procedure has four major blocks.
(1) Bisection search algorithm is used for optimizing the value of   (blue color in Figure 4).(2) Quasi MC sample generation block is used to incorporate process parameter variation or variation of the threshold voltage (  ) (red color in Figure 4).(3) Seevinck's rotation algorithm is used for SNM evaluation (green color in Figure 4).( 4) ANN block is used to optimize simulation time (yellow color in Figure 4).[21].This algorithm helps to evaluate the accurate value of the DRV by searching an optimum solution of   at which the SRAM cell fails.First, we define a rough range of   from 0 to 1 V based on the initial guess of the DRV.Suppose, if the range is defined as   1 and   2, the average between these two points is evaluated as    and this value is used in the analysis phase to evaluate the SNM of the SRAM cell.If the SNM point is evaluated as zero under PVs, it means that the failure has occurred, which implies that the DRV is situated above    and the point   1 is replaced with   .On the other hand, if the failure has not occurred, the DRV is located below    and   2 is replaced with   .The process is repeated as the   1 and   2 values get updated.It is continued until the difference Δ =   2 -  1 evaluates to be less than a defined tolerance (Tol = 0.001).Once this condition is met the process ends and the final value of   2 (or   1) is declared as the DRV.If the DRV is not located within the defined range, the process repeats for a new range.Table 1 represents the MOSFET constants assumed during the evaluation of SNM which is taken from the 45 nm Predictive Technology Model (PTM) [24].

Quasi MC Sample Generation.
The value of DRV largely depends on   of the transistors, T, and channel length (L).
Variation of these parameters affects the value of SNM and hence the DRV.We do the DRV evaluation only by varying   of transistors M1, M2, M3, and M4 as shown in Figure 2(b).These values are defined in a Gaussian range with particular mean and variance, and their samples are combined with the Quasi MC samples to obtain the seed points.We take 5000 Quasi MC samples for evaluation to get the better accuracy.
The SNM is evaluated for each of these seed points generated by Sobol sequence, and failure analysis is done accordingly.The variance of the Gaussian distribution is calculated by Pelgrom model [25,26], where  is the width of MOSFET and  can be used from Table 1.Since during hold mode only transistors M1, M2, M3, and M4 are active, we have employed the variation only for these transistors, which is calculated in Table 2.
where   and   are given by [27] where The subthreshold slope factor n is evaluated using (5) by evaluating subthreshold slope (S) [27], The value of S is found to be 60 mV/decade at room T = 25 ∘ C. Its value for typical bulk CMOS can range from 70 to 120 mV/decade [28].The value of n is evaluated as 1.042 using (5) at room T. The voltage at which node value Q equals QB is known as tripping voltage (  ).It is the point where curves (Q versus QB and QB versus Q) intersect, as shown in Figure 3(a).Here, we assume the identical cross-coupled inverters to evaluate   .The relation of   for an inverter is given by (6) (by ignoring the Drain Induced Barrier Lowering (DIBL) effects) as follows [29]: All the notations used for (6) are same as mentioned for (2), (3), (4), and (5).
We use the graphical technique proposed by Seevinck [22] to calculate the SNM value as shown in Figure 5.The steps involved in this techniques are as follows: (1) Obtain Q and QB samples using (2). Figure 6 shows the butterfly curve which is plotted using Q and QB samples for   = 0.5V.
(2) Combine Q and QB set into a matrix, X. ( New axis for the rotated curve is (U, V  ).V1 is the matrix corresponding to V  .
For a particular value of   and each and every sample of Quasi MC seed, the SNM is evaluated.

ANN
Δ< Tol ?using values of the previously conducted experiments.These values will be stored and is used for the upcoming analysis phase.
(ii) Analysis phase.After learning all the calculation procedure from the previous phase, the network is now ready for successfully providing outputs for any inputs provided.
For a 5000-sample space as mentioned in Section 2.2, the process of SNM evaluation is time-consuming.Hence, an ANN block which has been trained to evaluate the SNM is used.This block evaluates the SNM for all the samples and then separates the samples having low SNM (SNM < 0.02V).Only these samples are now sent to the actual analysis block where the accurate value of SNM is evaluated using rotation algorithm.
If the SNM = 0, the sample is declared as the failure sample.Input data set consists of   variations of M1, M2, M3, and M4 transistors and the   .SNM is the output vector as shown in Figure 8. Fifty data sets are generated using SNM evaluation algorithm, and the network is trained using Radial Basis Function (RBF) network, which is explained in next subsection.[23].An RBF network uses nonlinear functions to map inputs to the outputs into a high dimensional feature space.A general RBF network consists of three layers as shown in Figure 9.The input layer with inputs x  ( = 1, 2,. ..m)where  is a number of input parameters.The hidden layer is generated by one-to-one correspondence between the training input data   and the kernel function K(x,   ) for  = 1, 2, . ..N, where  is the number of training samples [23].In the third layer, the output is evaluated as the linear weighted sum of the kernel functions generated in the hidden layer.The following equations are used by the network:

RBF Network
(i) To evaluate kernel function  (  ,   ), where   ,   represent input vectors with , j = 1, 2, . ..m. Here,   denotes the Gaussian bandwidth.(i) Weight vector  is calculated by Here  is the kernel matrix,  is the identity matrix of order ,  is called the regularization parameter, and   is the desired response vector.
(ii) To evaluate output of the network , is the  th ( = 1, 2,. ... N) element of the weight vector  and (,   ) is the kernel function.Kernel used for the control technique is an Exponential Radial Basis Function (ERBF).By considering this ANN block, a considerable reduction in the evaluation time is observed.Four different ANN blocks are generated to evaluate the DRV for  = 15 ∘ C, 25 ∘ C, 50 ∘ C, and 100 ∘ C, respectively.

Result and Future Work
In this section, we present the results of an optimization based method which evaluates the DRV of a 6T SRAM cell incorporating the process parameter variation by considering the variation of   of four transistors.
DRV varies within a range and changes with each run of the experiment.It depends on the samples generated by Quasi MC simulation.To obtain the actual DRV, we conduct the experiment for 25 runs and the highest value obtained is considered as the DRV.After getting the DRV value from 25 experiments the corresponding histogram is plotted for two cases, (i) by considering the ANN block and (ii) by ignoring the ANN block.Table 3 indicates the   variation range for PMOS and NMOS transistors for 3, 4, and 5 variation.
Table 4 represents the DRV obtained at 3, 4, and 5 variation for T = 15 ∘ C, 25 ∘ C, 50 ∘ C, and 100 ∘ C, respectively, using the parameter specifications shown in Table 1 and the methodology followed in Section 2. From Table 4 we can observe that DRV increases with T slightly, while it increases significantly with the variation of   .To compare the time taken for DRV evaluation using with and without ANN block we run the MATLAB code at 25 ∘ C for 3 , 4 , and 5  variations and note the corresponding time taken for the highest value of DRV for 25 runs as shown in Table 5. Figure 10  However, the time taken for evaluation depends on the version of MATLAB tool, the machine on which the program is executing and how fast the failure sample is obtained out of the 5000 Quasi MC samples generated.From Table 5, we can observe that ANN block helps in reducing the time taken for DRV evaluation.Since the evaluation, time varies randomly for each run so the comparison of evaluation time cannot be generalized.The method can be extended to evaluate DRV for a memory chip with complex circuit structure.The modification can be made in the algorithm, to obtain the more accurate DRV results with better simulation time.Instead of obtaining the node voltage values using theoretical equations, practical SPICE-level simulation can be used to evaluate the SNM for a given   and   .Optimization algorithms can be implemented for the node voltages generated by the circuit.The procedure can be extended for other technology nodes by considering other process parameter variations like  and geometry variations in  and  for other cell topologies.

Appendix
See Figure 11.
(a) shows the butterfly curve plotted at   = 1V and Figure 3(b) shows the butterfly curve drawn by varying   .It can be observed from Figure 3(b) that the butterfly curve shrinks as the   is reduced and the SNM of the cell reduces to zero at   = 0.048 V.

Figure 3 :
Figure 3: Butterfly curve to obtain the SNM of 6T SRAM cell in hold mode (a) at   = 1V (b) by varying   .
represents the corresponding bar chart.The histogram to obtain the DRV at T = 15 ∘ C, 25 ∘ C, 50 ∘ C, and 100 ∘ C for 3 , 4 , and 5  variation follows the distribution shown in Figure 2(a) and has been presented in Appendix.

Table 2 :
The variance of V t variation () is calculated using (1).
0 ,  0 are mobility of NMOS and PMOS transistors, respectively,   ,   are oxide capacitance of NMOS and PMOS transistors, respectively,   ,   are width of polysilicon for NMOS and PMOS transistors, respectively, and L is length of polysilicon.
voltage,   ,   are subthreshold slope factor for NMOS and PMOS transistors, respectively,   ,   are drain current (when V GS = V t ) for NMOS and PMOS transistors, respectively,   is supply voltage,   ,   are threshold voltage of NMOS and PMOS transistors, respectively,

Table 3 :
V t variation range used for PMOS and NMOS.