This paper proposes a novel test generation algorithm based on extreme learning machine (ELM), and such algorithm is cost-effective and low-risk for analog device under test (DUT). This method uses test patterns derived from the test generation algorithm to stimulate DUT, and then samples output responses of the DUT for fault classification and detection. The novel ELM-based test generation algorithm proposed in this paper contains mainly three aspects of innovation. Firstly, this algorithm saves time efficiently by classifying response space with ELM. Secondly, this algorithm can avoid reduced test precision efficiently in case of reduction of the number of impulse-response samples. Thirdly, a new process of test signal generator and a test structure in test generation algorithm are presented, and both of them are very simple. Finally, the abovementioned improvement and functioning are confirmed in experiments.

For testing of integrated circuits (ICs) and system on chips (SoCs), both test accuracy and costs are important. On the one hand, it is not cost-effective to classify analog circuits subject to parametric faults if test application takes a long time along with increasingly rapid application of ICs and SoCs. On the other hand, it is difficult to apply traditional functional testing to ICs mixed with SOCs, as functions of which are too complex to test. Thus, this test generation algorithm is proposed as a new test strategy [

Analog test technology mainly includes two parts: test generation and fault diagnosis. There are many researches on fault diagnosis [

Analog test generation algorithm is mainly to introduce the concept of digital test generation into analog circuit test. The difference lies on the said analog circuit fault diagnosis method. The main purpose of analog test generation algorithm is to generate test signals necessary for fault diagnosis. Test signals here must be able to motivate fault. In other words, fault should be made to be detectable, so as to structure a fast and convenient online test platform. In recent years, fewer researches are engaged in analog circuit test generation. Pan and Cheng propose a cost-effective method to detect parametric faults in linear time-invariant (LTI) analog circuits in 1999 [

In order to solve the abovementioned problems, a new test generation algorithm based on extreme learning machine (ELM) [

The rest of this paper is organized as follows. Section

Basic structure of the test generation algorithm is to transform analog circuit test into digital field for analysis through digital-analogy and analog-digital converter. Normal state and various fault states of circuits can be regarded as an isolated state circuit. Circuits in different isolated states are sampled, so as to obtain abundant impulse response vectors. Then, impulse response vectors in normal state and fault state are separately identified, so as to establish different impulse response spaces. At last, a classifier is used to divide different sampling spaces. Test signals are obtained through calculation from trained classification hyperplane expression, so as to stimulate tested circuits. A comparison is made between output voltage and threshold value through a comparer, so as to realize fault diagnosis.

An overview of the test generation framework for LTI analog circuits is shown in Figure

Test generation framework.

Core steps of the test generation algorithm include two aspects: the one is to work out various classification hyperplanes and to figure out proper test signals as input of tested circuits according to classification features of state of various circuits (normal state and fault state); the other one is to analyze output of tested circuits after being stimulated by test signals and then judge any fault of such circuits. As shown in Figure

The first step is to build a response space constructed by many response vectors, which are constructed for each instance by sampling the analog circuit output signal. As the bandwidth (BW) is much smaller than the sampling frequency, there are a large number of impulse-response samples. In order to reduce costs, a new space of impulse-response is constructed by extracting the original space of sampled impulse-response [

As test generation for LTI analog can be viewed as one of several two-class classification problems, accuracy is important for each classification method. The SVM-based test generation algorithm has good classification accuracy [

In test generation, two-class classification shall be executed for

Test signals are obtained from classification hyperplane. The nonlinear classification algorithm is adopted for test generation in order to improve classification accuracy [

In order to determine whether circuit under test (CUT) passes or fails, we need an impulse as a threshold to compare test signals generated in Step

To solve the abovementioned problems that have been ignored in previous test generation methods, a new test generation algorithm based on ELM has been proposed in this paper.

The test generation algorithm proposed in this paper is based on the ELM, which is introduced as follows.

The ELM [

According to the above theories, ELM is different from other algorithms based on SLFNs, such as back propagation (BP) algorithm which contains five limitations:

For ELM, parameters of input layers are randomly chosen, while output weight vectors are obtained by calculating output matrix of the hidden layer, which is the Moore-Penrose generalized inverse of hidden layer output matrix. Therefore, only hidden nodes shall be assigned. Compared to SVM, ELM is advantageous from three aspects:

When classification accuracy is maintained, we need to build the new impulse-response space by sampling impulse responses for classification and then compress the original impulse response.

The main idea of [

Considering that there is an ideally selected impulse sampled space, select parts of elements equally from it. As shown in Figure

(a) Normal hyperplane classification; (b) hyperplane classification with supporting planes; (c) hyperplane classification with supporting planes in the case of compressing.

As shown in Figure

Based on the above analysis, in order to obtain better classification accuracy for different features, different trade-off parameters shall be introduced under relaxed conditions. For the sake of accuracy of the entire algorithm, contradiction between compressed samples and changed supporting planes can be eased more efficiently through experienced trade-off, by introducing different trade-off parameters under relaxed conditions.

Let us further discuss the changed trade-off parameters. The influence on trade-off parameters mainly comes from information loss because of compressing the sampled space. Therefore, methods can be applied to select sampled vectors with more information [

According to Huang’s theory, trade-off parameters are more sensitive to classification accuracy in SVM, lest squares support vector machine (LS-SVM), and ELM based on Gaussian kernel function, but are less sensitive to ELM based on both Sigmoid and multiquadric activation functions [

In the test generation, two-class classification shall be executed for

Time cost of classification algorithm is mainly caused by computational complexity. The number of impulse samples for classification is assumed to be

Computational cost of SVM mainly comes from calculation of the Lagrange multipliers

Therefore, in terms of computational complexity of learning algorithm, ELM-based classification algorithm is less time-consuming than SVM.

ELM includes two kinds of output functions, namely, the non-kernel based output function which maps

ELM is one of the best classification algorithms based on activation functions. Normal activation functions include Sigmoid function, hard-limit function, Gaussian function, and multiquadric function. According to analysis of compressing sample space, ELM based on both Sigmoid and multiquadric activation function is better than others. However, ELM based on Sigmoid activation function is better than that based on multiquadric activation function in terms of classification accuracy in circuit test. Therefore, the Sigmoid activation function suits ELM in circuit test.

In general, the non-kernel based ELM with Sigmoid activation function is suitable for algorithm proposed in this paper.

Considering input stimulation

In Formula (

Therefore, the coefficient of linear classification hyperplane

The ELM algorithm is not a linear classification algorithm. Therefore, test signal

We suppose that

If

Consider

According to the theorem in ELM, the learning process of

Formulas (

Based on the abovementioned analysis, learning algorithm proposed for test signal generation has obviously less computational complexity. And, in [

As Section

(a) Application of test sequence to DUT for classification. (b) Test structure of our proposed scheme. The entire test consists of

In general, one hyperplane is used to tell between one kind of parameter fault circuit and normal circuit. Multiple hyperplanes are required for discrimination in order to satisfy different kinds of parameters fault. Therefore, the simplified case of using one hyperplane for discrimination, which corresponds to one kind of parameters, can be easily extended to a case of using multiple hyperplanes which correspond to different kinds of parameter faults. In Figure

Upon a summary of above paragraphs, various parts and structural diagrams of the test generation algorithm based on ELM proposed in this paper are shown in Figures

Single fault structural diagram of the test generation algorithm based on ELM.

Multifault structural diagram of the test generation algorithm based on ELM.

Sample CUT with sampling frequency

Introduce ELM classifier and perform classification training for impulse response spaces in various states, so as to obtain various known parameters required, namely

Use DAC to stimulate CUT with the test sequence obtained in Step

Circuits always have multiple states, including normal state and multiple fault states. Therefore, there are always several values for

Circuit fault judgment via the analog circuit test generation algorithm always needs to operate Steps

This section illustrates ideas of this paper by simulation. The entire simulation is completed on a personal computer with a 3-GHz processor and 2-GB RAM. Programs used in simulation are developed by authors in MATLAB 7.1 and OrCAD 10.5.

ELM is one of the best classification algorithms based on activation functions. Without loss of generality, testing set misclassification of the test generation method is shown by circuits in Figure

(a) A three-pole active filter. (b) A two-pole active filter. (c) A five-pole active filter.

(a) Misclassification rates of ELM-based algorithm with different mapping functions for circuit in Figure

Each sampled vector of training sets is labelled as “passed” or “failed” according to circuit specifications. Testing set classification can be derived by setting the sign-bit of output response as zero. Furthermore, to determine effects of averagely compressed sample space, sampled vectors are established by averagely compressing previous impulse-response space, in which numbers of each sample and new impulse-response space are set to be 30 and 5, respectively. Here, trade-off parameters in different mapping functions are of default assignment. Figure

Figure

To compare with previous algorithms conveniently without loss of generality, three kinds of circuits are used in Figures

Figures

(a) Misclassification rates of SVM- and ELM-based algorithms for circuits in Figures

In order to facilitate comparison with previous algorithms in the case of compressing sampled space, two kinds of circuits are used in Figures

The sampled vector can be written as

Figures

(a) Misclassification rates of SVM- and ELM-based algorithms for circuit in Figure

In the case of compressing sampled space, for circuit in Figure

(a) Misclassification rates of different algorithms for circuit in Figure

The ELM-based, SVM-based, and CPSO-SVM-based algorithms are compared in Figures

This paper puts forward an advanced test generation algorithm for analog circuits. As described in Section

The authors declare that there is no conflict of interests regarding the publication of this paper.

This research is supported in part by NSFC (60934002, 61271035, 61201009, and 61071029) and specialized research fund for the DPHEC (20100185110004).