Complexity
Volume 2017 (2017), Article ID 7863095, 15 pages
https://doi.org/10.1155/2017/7863095

Research Article

CMOS Realization of All-Positive Pinched Hysteresis Loops

B. J. Maundy,¹ A. S. Elwakil,2,3 and C. Psychalinos⁴

¹Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, Canada T2N 1N4
²Department of Electrical and Computer Engineering, University of Sharjah, Sharjah, UAE
³Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza 12588, Egypt
⁴Physics Department, Electronics Laboratory, University of Patras, Rio, 26504 Patras, Greece

Correspondence should be addressed to B. J. Maundy; bmaundy@ucalgary.ca

Received 21 March 2017; Accepted 20 June 2017; Published 6 August 2017

Academic Editor: Jesus M. Munoz-Pacheco

Copyright © 2017 B. J. Maundy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.

1. Introduction

Pinched hysteresis was proposed to be a signature of memristive devices [1, 2], yet it can also be observed in several other nonlinear devices such as nonlinear inductors (capacitors) with quadratic-type current (voltage) dependence [3]. Finding a general model for pinched hysteresis behavior was attempted in [4] for specific devices labeled as memristors [5]. In [6] and from a simplified mathematical point of view, the following model was proposed and shown to exhibit a pinched hysteresis behavior which can fit both charge-controlled and flux-controlled memristance definitions:

where if and , the charge-controlled memristance is obtained, while for the alternative setting and , the flux-controlled memristance is obtained. In (1), the constants and are scaling and integration time constants, respectively. Note that circuit realization of this model for the purpose of emulating its pinched hysteresis behavior in non-solid-state devices requires a multiplier block, an integrator block, and an adder [6]. Several other emulator circuits have recently been proposed in the literature [7–13]. It is important to note that (1) is nonlinear due to the multiplication term and that pinched hysteresis cannot appear in a linear system. It is also possible to include other forms of nonlinearity that apply to the shaping of the loop as a result of shaping the applied excitation. This means replacing in (1) more generally with .

Pinched hysteresis loop is generally observed as a result of applying a bipolar sinusoidal voltage or current excitation signal and is thus symmetrical around the origin. Nonsymmetrical loops can also be obtained when the pinch point is shifted away from the origin. However, an all-positive pinched loop, to the best of our knowledge, has not been demonstrated before. It is the purpose of this work to introduce two simple circuits where this behavior is observed. We rely on the inherent nonlinearity of a MOS transistor to perform the multiplication operation required by (1) in order to obtain a charge-controlled memristance. Recall that a MOS transistor current-voltage relation can be described by

where is the drain-to-source current, and are, respectively, the gate-to-source and drain-to-source voltage, is the threshold voltage, and is a constant in units. It is obvious from (2) that a multiplication operation is inherent through the term . However, for an NMOS transistor, the current is unidirectional and the condition is necessary for the transistor to switch on. Therefore, if (2) is successfully reconfigured to implement (1), an all-positive pinched hysteresis loop can be obtained. In the first part of this work, we do not attempt to remove the extra nonlinear term and therefore it remains affecting the pinched loop. However, this effect is minimized via proper selection of the design parameters. In a later section of the work, we employ a linearization circuit to remove this quadratic term and hence ensure that only the multiplication nonlinearity term remains. As a result and comparing (2) to (1) assuming is minimized or eliminated, it is clear that the mapping , , and is necessary. To achieve this, we adopt a frequency-domain approach which also allows independent adjustment of the fixed part and the charge-controlled part of the memristance. We stress and clarify the role played by the capacitors in the proposed circuits, which is crucial to the understanding of pinched hysteresis behavior in general, as clearly seen in [17, 18] for solid-state devices as well. Note that, in reconfiguring (2) to realize (1) via this mapping, we are essentially modifying the MOS transistor transconductance such that it is state-controlled, with the state variable being the terminal voltage of the transconductance . The time constant necessary in (1) can only be obtained with an embedded capacitance (physical or parasitic) [17, 18]. Finally, it must be stated that this paper is concerned with the “pinched hysteresis behavior” as a behavior rather than with proposing yet another memristor emulator. The design concept of the circuits under study here is completely new and relies on a frequency-domain approach rather than a time-domain approach. It also shows for the first time that pinched hysteresis can even be unipolar, something not possible with memristors as they are so defined.

This manuscript is organized as follows. Section 2 looks at the proposed circuits and presents the theory behind their operation that leads to pinched hysteresis behavior. Section 3 computes the memristance of the proposed circuits, with numerical simulations, and presents pinch-off analysis of the proposed circuits. In Section 4, a method to linearize the main transistor in triode is presented which removes the extra nonlinear term in (2). In Section 5, simulation and experimental results are presented, and finally our conclusions are given in Section 6.

2. The Proposed Circuits

Consider the circuits shown in Figure 1 both consisting of opamp connected as a buffer and opamp along with the NMOS transistor as a simple voltage to current converter which converts the voltage of the noninverting terminal of into a current through NMOS transistor . It is essential for to remain in triode, hence acting as a transconductance. Both circuits contain a lossy integrator comprising , and a DC bias voltage required to maintain in triode (, ). The difference between the two circuits can be seen in their high-pass filter sections. In the case of Figure 1(a), it consists of with an additional DC source providing a DC voltage to the drain of . For Figure 1(b), the high-pass filter is made up of and here the drain-to-source DC biasing of comes from through as , where . Note that maintaining transistor in triode in both circuits requires that and for Figures 1(a) and 1(b), respectively.

(a)

(b)

Figure 1: The proposed nonlinear circuits with unipolar pinched hysteresis loop.

The lossy integrator of each circuit has a response given in the frequency domain which can be written as

where . Meanwhile, the high-pass filter in Figure 1(a) has a response

with , and likewise the response of the high-pass filter in Figure 1(b) is

where and . Clearly, both high-pass filters provide a leading phase shift by different amounts while DC biasing voltages are allowed to be passed on to the transistor to set . For an input voltage of amplitude and frequency in the form , it follows that the time dependent voltage of is

while the time dependent voltages in Figures 1(a) and 1(b) are, respectively,

where, for (7), and , respectively. Substituting (6)-(7) into (2) yields after considerable simplification

for Figure 1(a), and

for Figure 1(b). The coefficients of the and terms in (8) and (9) are given in Table 1. Note that, with the exception of , all coefficients in Table 1 are frequency dependent. This implies that it is necessary to choose proper values for time constants in order to observe the hysteresis behavior.

Table 1: Summary of the coefficients in (8) and (9) for Figures 1(a) and 1(b).

Coefficient
Figure 1(a)
Figure 1(b)

Close inspection of (8) under the assumption that shows that it can be rewritten in the dimensionless form

where represents an already phase shifted input signal. The term in the square brackets is clearly similar to (1) while additional and terms outside the brackets are unwanted and will result in a nonsymmetrical loop. Note that the offset terms and present are a result of the input being DC level shifted. However, using (10) and assuming that is sufficiently large such that the second and third terms are negligible and in addition translating the origin to , we obtain

which compared to (1) has the slightly modified form , where and .

Finally, in comparison with other circuits which also exhibit pinched hysteresis behavior and some of which are labeled as analog memristor emulators as shown in Table 2, about half of them use discrete multiplier blocks which are inefficient. By far, the vast majority use second-generation current conveyors with the only commercial one being the AD844, and several use additional hardware in the form of buffers, multiplexers, diodes, and switches. If the total component count is used as a figure of merit, then the proposed circuits of Figure 1 have the lowest count with their main drawback being operation in one quadrant. Note that even though our proposed circuits are listed among those identified as “memristors” or “memristor emulators,” we refrain from labeling our proposed circuits as “memristor emulators” and simply label them as among circuits having pinched hysteresis behavior.

Table 2: Summary of several analog circuits with pinched hysteresis and actual analog memristor emulators to date and their designs. MB: multiplier block; OPA: operational amplifier; CCII: second-generation current conveyors; AH: additional hardware, which may be in the form of buffers, multiplexers, diodes, inverters, switches, and so forth; I/D: incremental/decremental memristance emulation. The number (#) of transistors refers to the discrete number of external transistors. An OTA was used here in place of an OPA.

Reference [ ]
MB
OPAs
CCIIs
# of trans.
AH
Quadrant
I/D

[6]
1
—
3
—
Yes
2
Both

[7]
—

2
—
No
2
I

[8]
1
—
2
—
No
2
I

[9]
—
2
1
2
No
2
D

[10]
1
5
—
10
Yes
2
Both

[11]
—
2
1
1
No
2
I

[12]
—
—
3
1
No
2
I

[13]
1
2
—
—
Yes
2
D

[14]
1
—
2
—
Yes
2
I

[15]
—

1
2
No
2
Both

[16]
—
—
4
—
Yes
2
NA

This work
—
2
—
2
No
1
D

3. Charge-Controlled Resistance (Memristance) Calculation

Using (11) and setting , where is an arbitrary reference current and is an arbitrary scaling resistor, the memristance value for Figure 1(a) can be obtained as

where is the electrical charge. Note that since the input signal has a fixed , we can rewrite this memristance as

which has a fixed resistive part equal to and a charge-controlled part equal to . It is thus clear that while the transfer function controls the magnitude of both parts, can change the magnitude of the charge-controlled part alone. Note that this memristance is decremental [6]. Furthermore, note that, for sufficiently high frequency such that , and it follows that the fixed part of the realized memristance is approximately . However, for sufficiently high frequency such that , we also note that and therefore the realized memristance can be approximated as

We can further express the electrical charge as since the only capacitor in the circuit in this case capable of holding a charge is following the fact that . Accordingly,

where is the normalized (by ) voltage across . In a final step, we may freely express the period of the applied signal as a ratio of (i.e., ) leading to the simplified expression

if we select the arbitrary reference resistance as . Note that, for the condition to be satisfied, it follows that .

The expression in (16) is significantly important for two aspects:

(i)It shows that although the circuit has an all-positive input resistance, theoretically and according to (16), the memristance is not always positive. However, it remains positive because the origin has been already shifted to . With reference back to the origin , (16) then becomes

where . Figures 2(a) and 2(b) show the variation of the memristance versus the capacitor voltage and versus frequency , respectively. In Figure 2(a), for the values chosen: ,  V V V, and  mA/V², we obtain  kΩ. Correspondingly, selecting a suitable reference current such as  mA leads to a nominal value for of 6.7 kΩ (i.e.,  V). For Figure 2(b), we fixed  V and  μF and show the decremental nature of the memristance whereas the frequency increases when asymptotically approaches .(ii)It highlights the significance and necessity of the existence of a capacitor in order to hold the charge. In this circuit, this capacitor is ; however, in solid-state devices, this capacitor may well be a parasitic capacitor or equivalent of parasitic capacitances as observed in [17, 18]. It thus appears to the authors that it is not possible to isolate the appearance of pinched hysteresis loops from the existence of a capacitive effect.

In a similar manner, the memristance of the circuit in Figure 1(b) can be obtained as

which unlike (13) has a fixed resistive part equal to but an identical charge-controlled part. Noting that for and making the same assumptions as before, a generalized expression for can be given as

where .

(a)

(b)

Figure 2: (a) Plot of memristance versus capacitor voltage when ,  kΩ,  kΩ, and . (b) Plot of versus frequency when  μF.

3.1. Numerical Simulations

Sample Matlab plots of (8) and (9) are shown in Figures 3(a)–3(c) to normalized values of  mA/V² V V, and  V. In the first of the plots shown in Figure 3(a), , with and the applied sinusoidal voltage frequency and  V. Note that having is equivalent to setting and that . In this figure, we see that neither loop is symmetrical which is attributed to the and terms (see (10)) and the phase shift term introduced by the lossy integrator. In the second plot, shown in Figure 3(b), , with and  V as before but . The pinched loops from the two circuits are nearly identical and the upper lobe is far bigger than the lower one. In Figure 3(c), , with ,  V, and . Clearly, as or decreases, the upper lobe decreases in size and the pinch point increases. Note the reduced value of for the circuit (Figure 1(a) or (8)). This implies that the circuit of Figure 1(a) must work with reduced input amplitudes compared to the circuit of Figure 1(b), unless and are adjusted in tandem. This is not the case for the circuit of Figure 1(b) where DC bias voltages are related by which is fixed for .

(a)

(b)

(c)

(d)

Figure 3: Matlab simulation of the I-V characteristics of Figures 1(a) and 1(b) as given by (8) and (9), respectively. (a) , with . (b) , with . (c) , with and  V. (d) , with ,  V, and  V and  V for Figures 1(a) and 1(b), respectively.

Finally, in Figure 3(d), with , , , and  V. Under these conditions, , and decreased amplitudes must now be used in the circuit of Figure 1(b) or (9) compared to the circuit of Figure 1(a) or (8). Therefore, we select  V and  V for the two circuits, respectively, in this case.

3.2. Pinch Point Analysis

The unique form of (8) and (9) allows for a closed-loop solution of the pinch-off point in these circuits. It can be shown after considerable simplification that (8) and (9) have a pinch-off point given by

where

and the subscripts refer to (8) and (9), respectively. The frequency dependent nature of (20) makes their analysis difficult; however, several observations can be deduced. First, can be positive or negative depending on the values of , and as observed in Figure 3. In addition, plays an important role even though it is not the main charge holding or integrating capacitor. In Figure 1(a), its minor role is to block as is passed, but in both circuits, its main contribution is to add a leading phase shift opposed to the lagging phase shift caused by . For example, in the circuit of Figure 1(b), in the absence of , that is, if , then , because , and with , (21) reduces to , setting . That is, no pinch point will occur.

Secondly, under the assumption , we find that when or when . Under this condition, remains in triode so long as which is easily satisfied. For the general case when , implying that (unless ), the general solution to yields

Likewise, the value for in the circuit of Figure 1(b) that results in can be expressed as

In both general cases, (22) and (23) are frequency dependent, the exception being when for (22), but both can be minimized for frequency dependance by ensuring that , , and . Sample plots of the I-V characteristic for the circuit of Figure 1(a) governed by (8) to the conditions  V,  μs,  V,  V,  mA/V², and  V are shown in Figure 4(a).

(a)

(b)

Figure 4: (a) Matlab simulation of the I-V characteristic of Figure 1(a) governed by (8) to  V,  μs V,  V,  mA/V², and  V. (b) Input voltage and current plotted as a function of time at a frequency of  rad/s.

Note that because and , is independent of the input frequency which is verified at the three frequencies  Hz, as theoretically predicted. In Figure 4(b), and are plotted as a function of time.

Finally, no pinch point occurs when or and if this happens at the two frequencies :

Furthermore, if , a unique frequency at which no pinch point exists is

In the case of Figure 1(b), no easy closed-loop form of the solution exists, but when the frequencies at which the pinch point occurs can be obtained by numerically solving, for , the equation

when or

when , where

4. Linearization of

It is possible to reduce the distortion in as a result of the term in (2) by a number of techniques. One such technique is bisection of the input range first popularized by [19–21] and exploited by many others. Consider therefore the circuit shown in Figure 5 where is replaced by transistors . Voltages and form the output voltages of the lossy integrator and high-pass filters, respectively. Transistors are identical in size as are and . Transistors and are to function as an adder as first proposed by [22] in the use of low voltage multipliers. Under the correct bias conditions, it follows that , and then given that both and have the same and each drain current is governed by and , the total current through and simplifies to or an equivalent resistance of . Under these conditions, (8) and (9) change to

and for Figure 1(b)

where the new coefficients , and are given in Table 3. Comparing (8)-(9) with (29)-(30) and likewise Tables 1 and 3, one notices fewer terms for the linearized resistor, with coefficients and . In addition, both and , with all other terms in the coefficients being equal. The corresponding new pinch point is given by

where

The benefits to linearizing are immediately clear upon close inspection of (31)–(33). In particular, for the circuit of Figure 1(a) in the general case when , the general solution to now yields

which, for , implies that, for , is chosen such that . Of course, under these conditions, the composite linearized resistor is at the edge of the triode and a more practical solution would be for a given , , and to simply choose . For the circuit of Figure 1(b) employing a linearized , the choice of does not affect the pinch point; however, the value of that results in is given by

which is still frequency dependent, but minimization is still possible if , , and . Last but not least, no pinching occurs for the circuit of Figure 1(a) using the linearized resistor at frequencies

assuming and at

Table 3: Summary of the coefficients of the input current of Figures 1(a) and 1(b) in response to an input voltage when is replaced by a linearized resistor such as the one shown in Figure 5.

Coefficient
Figure 1(a)
Figure 1(b)

Figure 5: An improved linear resistor obtained by replacing in Figure 1 with transistors .

for the circuit of Figure 1(b) when .

5. Simulation and Experimental Results

The circuits in Figures 1(a) and 1(b) were simulated and built experimentally. In the sections that follow, simulations of Figures 1(a) and 1(b) without and with linearization of were conducted. For the experiments, off-the-shelf discrete components were used without linearization of .

5.1. Simulation Results: Without Linearization

For simulation purposes, Cadence was used employing the Design Kit offered by the AMS 0.35 μm CMOS process. The opamp utilized in simulations is demonstrated in Figure 6, where the bias scheme was  V and  μA. The MOS transistors’ aspect ratio is given in Table 4 with  Ω and  pF to achieve a phase margin of . Also, the aspect ratio of transistor in Figure 1(a) was 100 μm/1 μm; for , the aspect ratio was 12 μm/2 μm and thus its gain factor was  mA/V².

Table 4: MOS transistors’ aspect ratio for Figure 6.

Transistor

50 μm/2 μm

100 μm/2 μm

200 μm/0.5 μm

50 μm/0.5 μm

200 μm/0.5 μm

Figure 6: Opamp used in simulations.

The resistor and capacitor values used in simulations were 820 Ω and  nF and, therefore, . The DC voltages were  V and  V. Considering a sinusoidal input with 700 mV amplitude and variable frequency, the obtained characteristics, for 600 Hz, 1 kHz, and 1.5 kHz, are demonstrated in Figure 7. The time-domain behavior of the scheme in Figure 1(a) is demonstrated in Figure 8 for a 1 kHz input voltage. Likewise, the obtained characteristics, for Figure 1(b) for 400 Hz, 700 Hz, and 2 kHz, are demonstrated in Figure 9 with the corresponding time-domain behavior shown in Figure 10 for a 700 Hz input voltage.

Figure 7: Simulated characteristics for 600 Hz, 1 kHz, and 1.5 kHz.

Figure 8: Time-domain behavior of the circuit in Figure 1(a) for 1 kHz.

Figure 9: Simulated characteristics for 400 Hz, 700 Hz, and 2 kHz.

Figure 10: Time-domain behavior of the circuit in Figure 1(b) for 700 Hz.

The effect of in the operation of the topology in Figure 1(b) has also been studied under the conditions , which sets , respectively. The derived characteristics, for 700 Hz, are given in Figure 11.

Figure 11: Simulated characteristics for .

5.2. Simulation Results: With Linearization

The improved linear resistor shown in Figure 5 was also used for linearizing transistor . The power supply voltage was equal to 2 V and the aspect ratio of and was 1 μm/2 μm, while for it was 3.2 μm/2 μm. Considering a sinusoidal input with 700 mV amplitude and variable frequency, the obtained characteristics, for the circuit in Figure 1(a), derived at the same conditions as in the previous subsection, and for 600 Hz, 1 kHz, and 1.5 kHz, are demonstrated in Figure 12. The corresponding time-domain behavior is depicted in Figure 13 for a 1 kHz input voltage.

Figure 12: Simulated characteristics for the circuit in Figure 1(a) with 600 Hz, 1 kHz, and 1.5 kHz and linearization of .

Figure 13: Time-domain behavior of the circuit in Figure 1(a) for 1 kHz and linearization of .

In a similar way, the plots for the circuit in Figure 1(b), obtained at the same conditions as in the previous subsection, are given in Figure 14. The time-domain behavior is given in Figure 15 for a 700 Hz input voltage.

Figure 14: Simulated characteristics for the circuit in Figure 1(b) with 400 Hz, 700 Hz, and 2 kHz and linearization of .

Figure 15: Time-domain behavior of the circuit in Figure 1(b) for 700 Hz and linearization of .

5.3. Experimental Results

In the first of a series of experimental tests, the circuit of Figure 1(a) was constructed using 741 opamps powered by a ±15 V supply. The resistor and capacitor values used were  Ω and  nF ensuring that . Transistors and were taken from Fairchild’s dual complementary pair CD4007CN chip. The DC biasing voltages used were  V,  V, and . The current was measured by inserting a resistor in series with and measuring the voltage drop across this resistor using an instrumentation amplifier with a gain of 10; that is, . The results of versus are shown in Figure 16 for several frequencies starting at 1 kHz with the pinch point remaining nearly constant for  V. Note that this result is consistent with (22) where SPICE models for the CD4007 (the actual value of is both foundry and process dependent but unfortunately actual data on the CD4007CN chips used was not available) place in the order of around 2~2.3V. Bending of the lobes can be observed towards a downward trend when the frequency is decreased below 1 kHz and upwards when the frequency is increased above 1 kHz. The usable range of this circuit was found to be from 300 Hz to 10 kHz. Note that the lower frequency limit on the operation of the circuit (300 Hz) is also consistent with (25) where, for ,  Ω,  nF, with , yields a calculated value of 292 Hz. The upper frequency limit was observed when the lobes of the pinch hysteresis were too close to be distinguishable and in addition would also be set by limitations associated with losing gain in its closed-loop configuration with .

(a)

(b)

(c)

(d)

Figure 16: (a) Experimental results of the plot of and at 1 kHz for the circuit of Figure 1(a). (b) Oscilloscope trace of the pinched hysteresis loop of the memristor emulator circuit of Figure 1(a) at 1 kHz, (c) at 600 Hz, and (d) at 1.5 kHz.

In a second experimental test, the circuit of Figure 1(b) was set up and the resistor and capacitor values used were 2 kΩ and  nF ensuring that . The current was likewise measured through a resistor using an instrumentation amplifier set to a gain of . Resistor was adjusted by a potentiometer at a value of  Ω which set . Input voltages were set at  V and and the initial frequency was set at 700 Hz. The results shown in Figure 17 indicate that the pinch point and symmetry of the lobes are highly dependent on the input frequency. For this configuration, pinching was lost for frequencies below 300 Hz and above 10 kHz.

(a)

(b)

(c)

(d)

Figure 17: (a) Experimental results of the plot of and at 700 Hz for the circuit of Figure 1(b). (b) Oscilloscope trace of the pinched hysteresis loop at 700 Hz, (c) at 400 Hz, and (d) at 2 kHz.

Finally, it should be mentioned that the circuits of Figures 1(a) and 1(b) were also tested using different time constants such as and and all results not shown here were consistent with the expected theory.

6. Conclusion

Two simple nonlinear circuits that exhibit unipolar pinched hysteresis behavior were presented in this paper. The multiplication-type nonlinearity between a state variable and its past history, as given in (1), is fundamental in obtaining pinched hysteresis although the past history can also be replaced by the rate of change of the present state as shown in [3]. In this work, this multiplication is simply achieved using the MOS transistor transconductance equation. The proposed circuits have been analyzed, their pinch points were determined, and their behavior was verified in Matlab and experimentally. A method of linearization that enables the elimination of undesired higher-order nonlinear terms was also examined and verified via simulations in Cadence. Of significant importance in this work is the clarification of the role played by the charge holding capacitor in the value of the charge-controlled memristance. We argue that, in all solid-state devices that have been fabricated and that show pinched hysteresis, a parasitic capacitor combined with a modulation-type (multiplication-type) nonlinearity is behind the appearance of this behavior. Arguably, the authors of [18] conclude that both “memory resistance and memory capacitance must coexist.”

Conflicts of Interest

The authors declare that they have no conflicts of interest.

Acknowledgments

The authors would like to acknowledge the support of the Natural Sciences and Engineering Research Council (NSERC) of Canada in this work and Mr. Abdulwadood Al-Ali in the preparation and the carrying out of the experiments.

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