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This brief leads the synthesis of fractional-order memristor (FOM) emulator circuits. To do so, a novel fractional-order integrator (FOI) topology based on current-feedback operational amplifier and integer-order capacitors is proposed. Then, the FOI is substituting the integer-order integrator inside flux- or charge-controlled memristor emulator circuits previously reported in the literature and in both versions: floating and grounded. This demonstrates that FOM emulator circuits can also be configured at incremental or decremental mode and the main fingerprints of an integer-order memristor are also holding up for FOMs. Theoretical results are validated through HSPICE simulations and the synthesized FOM emulator circuits can easily be reproducible. Moreover, the FOM emulator circuits can be used for improving future applications such as cellular neural networks, modulators, sensors, chaotic systems, relaxation oscillators, nonvolatile memory devices, and programmable analog circuits.

Resistors, inductors, capacitors, and memristors are basic network elements and the real behavior of each of them is time-varying and nonlinear [

A challenge at fractional calculus is the building or in best of cases, the approximation of fractances [

Given

Choose

Using the numerical value of

Frequency denormalization is done for

FOI circuit synthesis based on CFOA.

Following these steps and from (

Numerical values of the phase and magnitude response of IOI, FOI, and FOI with

| Phase (Deg) | Magnitude (dB) | ||||||
---|---|---|---|---|---|---|---|---|

IOI | FOI | FOI with | Difference | IOI | FOI | FOI with | Difference | |

0.99 | | | | | | | | |

0.75 | - | | | | - | | | |

0.5 | - | | | | - | | | |

0.25 | - | | | | - | | | |

1 m | - | | | | - | | | |

Transient responses of IOI, FOI, and FOI with

Behavior of IOI (black line), FOI for:

In [

Riemann-Liouville and Caputo fractional integral

or Grunwald-Letnikov fractional integral

where for both fractional integrals,

(a) Flux-controlled floating fracmemristor and (b) charge-controlled grounded fracmemristor.

Defining the fractional-order flux

Once the behavioral model for each floating and grounded fracmemristor at its incremental and decremental version has been deduced, numerical simulations can be realized. Henceforth, numerical results of the incremental topologies will be shown below in the left-side and for the decremental topologies will be shown in the right-side. On the one hand, to design the integer-order floating memristor working at incremental and decremental mode, the design guideline reported in [

Component list of Figure

Element | Figure | Figure 1 in [ | Figure | Figure 5 in [ | Tolerance | ||||
---|---|---|---|---|---|---|---|---|---|

Inc. | Dec. | Inc. | Dec. | Inc. | Dec. | Inc. | Dec. | ||

| −37 mV | −75 mV | −40 mV | −70 mV | −49 mV | −50 mV | |||

| 36 mV | 76 mV | 39 mV | 85 mV | −50 mV | −93 mV | −95 mV | ||

| 2 V | ||||||||

| ±10 V | ||||||||

| |||||||||

| 10 kΩ | 9 kΩ | ±5% | ||||||

| 1 kΩ | 10 kΩ | 11.5 kΩ | ||||||

| - | 2.4 kΩ | - | 9.5 kΩ | |||||

| 10 kΩ | - | - | ||||||

| 10 kΩ | - | 10 kΩ | - | |||||

| 2 M | - | 2 M | - | |||||

| |||||||||

| 10 pF | - | 10 pF | - | ±20% | ||||

| 2 nF | - | 2 nF | - | |||||

| - | 2 nF | - | 2 nF |

Comparing the frequency-dependent pinched hysteresis loops of the flux-controlled floating memristor (blue line) and fracmemristor (red line): (a) incremental mode, (b) decremental mode, and for the charge-controlled grounded memristor (blue line) and fracmemristor (red line): (c) incremental mode and (d) decremental mode.

Once obtained the hysteresis loops of the floating and grounded fracmemristor in both operation modes and for

Component list of Figure

Element | | | | | |
---|---|---|---|---|---|

| 10 k | ||||

| 2 M | ||||

| 10 pF | 0.28 nF | 0.66 nF | 1.2 nF | 2 nF |

| 2 nF |

Fractional-order frequency-dependent pinched hysteresis loops of the floating fracmemristor operating at (a) incremental mode and (b) decremental mode. For the grounded fracmemristor operating at (c) incremental mode and (d) decremental mode. For all cases:

Incremental and decremental fracmemristance variation when a pulse train (bottom graphics) is applied to (a) Figure

A synthesis methodology for obtaining the behavior of FOM emulator circuits from integer-order memristor emulator circuits at their versions floating and grounded and operating at incremental and decremental mode has been described. Basically, the methodology consists of exchanging the IOI circuit clearly defined in the integer-order memristor emulator circuit by an FOI circuit, so that not only an FOM is obtained, but also the synthesized topology is not drastically modified with respect to its original topology. In each fractional topology, a mechanism of offset compensation in order to push or pull the crossing point of the hysteresis loops towards the origin was used [

Experimental and simulation data along with source files can be obtained through a letter sent to first author, explaining their intended use.

The authors declare that they have no conflicts of interest.

This work was supported in part by the Proyecto Apoyado por el Fondo Sectorial de Investigación para la Educación of the National Council for Science and Technology (CONACyT), Mexico, under Grant 222843; in part by the Universidad Autónoma de Tlaxcala (UATx), Tlaxcala de Xicohtencatl, TL, Mexico, under Grant CACyPI-UATx-2017; and in part by the Program to Strengthen Quality in Educational Institutions, under Grant C/PFCE-2016-29MSU0013Y-07-23.