A novel generic memristor, dubbed the

Memristor, the acronym of memory resistor, is one of the most propitious elements in the emerging memory sector due to its exclusive attributes under DC or AC excitations, as well as its miniature nanoscale physical dimension. Extensive research is ongoing on memristors and the memristive system after the seminal paper published by

Recently, several researchers investigated the multistate phenomena in generic and extended memristors [

Another feature of this type of multistate corsage memristor is the alteration of the stable equilibrium states. In this case, a sufficiently large amplitude with short pulse width or a minimum pulse amplitude with lengthy pulse width is applied across the memristor to switch the state from one stable equilibrium state to another stable state by converging into the basin of a new stable attractor. In this way, the equilibrium state of a multistate corsage memristor is changed to a new stable state where the resistances or conductances of each stable equilibrium state are distinguishably different from each other [

In this paper, we demonstrate a novel quad-stable generic memristor, dubbed the

In addition to the theoretical insights, we have designed and built a real emulator circuit of the proposed corsage memristor. For the physical realization of the piecewise linear 6-lobe Chua corsage memristor, we use the Graetz bridge [

The rest of the paper is organized as follows: the 6-lobe corsage memristor is designed and introduced in Section

The

The frequency-dependent pinched hysteresis loops of a device, when driven by any periodic input current or voltage source with a zero DC component, are a signature of a memristor or memristive system [

Frequency-dependent pinched hysteresis loop fingerprint of the 6-lobe Chua corsage memristor, calculated with initial state

The dynamic route of a nonlinear system prescribes the dynamics of nonlinear differential equations [

Dynamic route map of the 6-lobe Chua corsage memristor at

The arrowheads in Figure

Figure _{1}), _{2}), _{3}), _{4}), _{5}), _{6}), and _{7})_{1}, _{3}, _{5}, and _{7} are stable whereas _{2}, _{4}, and _{6} are unstable equilibrium points because the state variable _{2}, _{4}, and _{6}. Moreover, the equilibrium points _{1}, _{3}, _{5}, and _{7} in Figure _{2}, _{4}, and _{6} are unstable as the eigenvalues are positive [

Figure _{2}, _{4}, and _{6} converge to stable equilibrium points _{3}, _{5}, and _{7}, respectively, to their right as shown with purple arrowheads. In contrast, for any initial state _{2}, _{4}, and _{6} converge to stable equilibrium points _{1}, _{3}, and _{5}, respectively, to their left as shown with black arrowheads.

The phase portrait of stable equilibrium states _{1}, _{3}, _{5}, and _{7} is shown in Figure _{2}, _{4}, and _{6}, respectively. Similar to Figure _{3}, _{5}, and _{7}, respectively, as shown with purple arrowheads. Conversely, for _{1}, _{3}, and _{5}, respectively, as shown with black arrowheads.

Phase portrait of the stable equilibrium states _{1}, _{3}, _{5}, and _{7}_{2}, _{4}, and _{6}, respectively.

The dynamic routes in Figure

The more stable equilibrium states of the 6-lobe corsage memristor increases the memory efficiency per device 50% and 25% compared to 2-lobe and 4-lobe corsage memristors, respectively, and eventually enhance the capability to represent a desired function more closely than 2-lobe or 4-lobe corsage memristors.

In mathematics, parametric representation of an object is a collection of parametric equations which are used to express the coordinates of the points that make up a geometric object [

The parametric representation of the 6-lobe Chua corsage memristor can be derived by equating state (

The DC voltage of the proposed corsage memristor is given explicitly by

The parametric representation of the DC current of the 6-lobe corsage memristor can be derived by substituting _{0} = 10^{−6}, namely,

The parametric representations of the proposed corsage memristor are shown in Figure

Parametric representations of the 6-lobe Chua corsage memristor (a) voltage

For convenience of readers, several points of the parametric representation of

Numerical values of the 6-lobe corsage memristor obtained from parametric representation over −12 ≤

−12 | −15 | −2.16 |

0 | −3 | 0 |

3 | 0 | 0 |

6 | 3 | 0.11 |

9 | 0 | 0 |

10 | −1 | −0.1 |

12 | −3 | −0.43 |

15 | 0 | 0 |

20 | 5 | 2 |

25 | 0 | 0 |

30 | −5 | −4.5 |

35 | 0 | 0 |

40 | 5 | 8 |

42 | 7 | 12.35 |

49 | 0 | 0 |

50 | −1 | −2.5 |

56 | −7 | −21.95 |

60 | −3 | −10.8 |

63 | 0 | 0 |

70 | 7 | 34.3 |

78 | 15 | 91.26 |

A circuit-theoretic approach is used to derive the DC

For each value of

Then we determine the DC current

Finally, we draw the DC

The DC _{1}), _{2}), _{3}), _{4}), _{5}), _{6}), and _{7}). As the values of the state variable of each DC

DC

One of the most important features of the 6-lobe corsage memristor is the contiguousness of its DC

Another impressive feature is that the parametric representation and the DC

The

The switching kinetics of the 6-lobe Chua corsage memristor can be represented through its

The appropriate pulse amplitude

The derived universal formulas in (

The dynamic route map (DRM) in Figure _{1} to low-resistance (high conductance) state _{5}. To switch from _{1} to _{5}, we choose the pulse amplitude _{A}_{1} to _{5} and converges to memory state _{3}. However, pulse width _{1}(_{01}) to

Memory state switching kinetics of the 6-lobe Chua corsage memristor from memory state _{1} to _{5} for an input square pulse

The total time period _{1} to _{5} is expressed as

The memory state switching from _{1} to _{5} in Figure _{A}_{1} (_{1} on the red curve to a point directly above _{1} on the blue curve (yellow circle) at _{5} (

The exponential trajectories of the _{5} from _{1} is the summation of all the time periods needed for an individual trajectory to propagate through the piecewise linear segments which is

To switch back from the low-resistance (high conductance) state _{5} to the high-resistance (low conductance) state _{1} of our corsage memristor, we simply applied a negative voltage pulse with amplitude _{A}_{5} to _{1} is shown in Figures _{1} (_{1} memory state. To switch back from _{5} to _{1}, the total time

Switching kinetics from low-resistance state _{5} to high-resistance state _{1} for an input square pulse

The pulse amplitude _{1} to _{5} with a different pulse width _{3} (_{5} (_{4} (_{4} (_{3}, and in this case, the state variable _{3} (_{Δw}(_{4}.

Switching failures of the 6-lobe corsage memristor from _{1} to _{5} for a pulse amplitude

For convenience of the readers, we plotted the hyperbolic relationship between _{1} and _{5} of our 6-lobe corsage memristor as shown in Figure

Relationship between the pulse amplitude

For physical realization of the 6-lobe Chua corsage memristor, we modified the circuit in Figure

Circuit diagram of the real 6-lobe Chua corsage memristor emulator with quad-stable input dynamics.

The _{0} in Figure _{0}, we applied the circuit-theoretic analysis on an op-amp circuit [

Circuit diagram of nonlinear resistor _{0} of the real 6-lobe corsage memristor using off-the-shelf components.

The active and locally active two-port (marked with the black box) in Figure _{41}, _{42}, and _{43}) which determine the effective saturation voltage

Region-based ideal models of the op-amp circuit: (a) Linear region, (b) +Saturation region, and (c) −Saturation region.

The Linear region of the op-amp circuit in Figure

The following relation between output voltage

Pedagogically, in the linear region, the relation between the saturation voltage (±

The loop

For the +Saturation region shown in Figure

The current for the

For the

The current

Plotting the output voltage _{33} = 1K, _{43} = 1K, _{63} = 100K, _{73} = 1K, and _{sat} = 14 V over the input voltage range −14 V ≤ _{03} increases proportionately to the input voltage

Mathematical simulation of input currents (

Similarly, following the circuit-theoretic concepts mentioned above, the input currents

The loci of

The total current

The six-breakpoint

DC current

The mathematical simulation presented in Figure

The nonlinear resistance waveform obtained from the SPICE modelling in Figure _{01}, _{02}, _{03}, and _{04} where _{01} = (_{0} = 147.47 _{02} = (147.47 Ω < _{0} ≤ 216.07 Ω), _{03} = (216.07 Ω < _{0} ≤ 336.10 Ω), and _{04} = (_{0}> 336.10 Ω).

Similar to the SPICE model, the mathematical and the circuit implementation plots of _{0} at the −2.16 V < _{0} = 137 Ω. The fluctuation was induced due to computational difficulties at

The breakpoints of the

Although the breakpoints of the DC

The SPICE simulation of switching of memory states of the real 6-lobe Chua corsage memristor emulator (in Figure _{01} and _{03}. To switch from _{01} to _{03}, a pulse input _{03} = (216.07 Ω < _{0} ≤ 336.10 Ω) which confirms the successful switching from memory state _{01} to _{03} for an input pulse

Switching kinetics of the memory states of real 6-lobe Chua corsage memristor emulator. (a) Successful switching: the corsage memristor emulator switches from memory state

In this paper, we also demonstrate the switching failure scenario of the real 6-lobe Chua corsage memristor as shown in Figure _{02} = (147.47 Ω < _{0} ≤ 216.07 Ω) which confirms the failure of switching as our intention is to switch from memory state _{01} to _{03} for an input pulse _{02}.

The switching failure scenario gives us the insights that the emulator circuit of our proposed corsage memristor is also dependent on the appropriate pulse amplitude and the pulse width like its mathematical model. To illustrate the relationship of pulse amplitude and the pulse width in our real emulator circuit, we plot the _{A} versus pulse width |_{A}

Relation between amplitude

The recent interest in inherently nonlinear memristor devices is bringing to a new life to the theory of nonlinear circuits and systems. In this paper, we design and build a highly nonlinear novel device, namely, the 6-lobe Chua corsage memristor, and its real emulator circuit using the nonlinear circuit theory. The proposed generic memristor can be used as a multistate, specifically 4-state, memory device with an increased efficiency of 50% compared to the 2-lobe and bistable extended memristor whereas the efficiency of the proposed memristor increased by 25% compared to the 4-lobe corsage memristor. Moreover, due to the presence of more equilibrium points compared to the 2-lobe or 4-lobe corsage memristors, the proposed corsage memristor exhibits a higher variety of dynamic routes in response to different initial conditions

The data used to support the findings of this study are available from the first author or corresponding author upon request.

The authors declare that they have no conflicts of interest.

The authors would like to thank Professor Leon Chua for his wonderful assistance for revising the manuscript and technical advice. This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korean Government (2016R1A2B4015514), the “Cooperative Research Program for Agriculture Science and Technology Development (Project no. PJ0120642016),” the Rural Development Administration, Republic of Korea, and the US Air Force Office of Scientific Research under Grant no. FA9550-18-1-0016.

Finding of universal formulas. Figure