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In this paper, a fully integrated memristor emulator using operational amplifiers (OAs) and analog multipliers is simulated. Based on the fully integrated memristor, a scroll-controllable hyperchaotic system is presented. By controlling the nonlinear function with programmable switches, the memristor-based hyperchaotic system achieves controllable scroll numbers. Moreover, the memristor-based hyperchaotic system is fully integrated in one single chip, and it achieves lower supply voltage, lower power dissipation, and smaller chip area. The fully integrated memristor and memristor-based hyperchaotic system are verified with the GlobalFoundries’ 0.18 ^{2}.

Memristor and multiscroll chaos systems are two research hotspots in recent years. Although, memristor is not commercially available, many memristive emulators have been reported [

Most of the existing memristive emulators and memristor-based chaotic circuits are realized using commercially available off-the-shelf discrete components with breadboard or field programmable gate array (FPGA). The breadboard or FPGA-based chaotic circuits are difficult to achieve low-voltage and low-power conditions. As we all know, the fully integrated circuits have the advantages of lower supply voltage, less power consumption, more stable and convenient than their breadboard-based counterparts. Cruz and Chua [

In order to realize more practical and complicated integrated memristor-based chaotic circuits, a fully integrated memristor emulator and a scroll-controllable hyperchaotic system are presented and verified in this paper. The Cadence IC Design Tools post-layout simulation results verify that the presented fully integrated memresistor and memristor-based scroll-controllable hyperchaotic system are all feasible and achievable and the fully integrated method will further promote the practical applications of chaotic circuits and systems.

In a fully integrated chaotic system, complex and high-performance OA is not necessary, and the designed low-voltage and low-power two-stage OA with simple structure for the fully integrated chaotic system is presented in Figure _{7}–M_{9} [_{10}–M_{11} consist of a double-ended input single-ended output differential input stage; M_{12} and M_{13} consist of the second common source amplifier stage; M_{14} and capacitor _{1}–M_{6} consist of the bias circuit of the OA.

The designed OA.

The simulated amplitude and phase-frequency characteristics of the operation amplifier are presented in Figure _{0}–M_{3}, it is clear that the voltage gain of the operation amplifier is about 30 dB, its 3 dB bandwidth is 218.5 kHz, and the phase margin is about 86.22°. Its static power consumption is about 5.85 mW with ±2.5 V supply voltage.

The amplitude and phase frequency of the OA.

The analog multiplier used in the memristor is presented in Figure _{5} consist of the transconductance stage; M_{6}–M_{9} consist of the Gilbert switch stage, and M_{10}–M_{13} consist of the load stage of the analog multiplier. The supply voltage of the designed analog multiplier is

The designed analog multiplier.

The transient responses of the designed analog multiplier are presented in Figure

The transient response of the analog multiplier.

Memristors could be classified as flux-dependent and charge-dependent memristors. A fully integrated flux-controlled memristor is adopted in this work, and its circuit realization using operation amplifier and multipliers is presented in Figure

The fully integrated memristor.

The voltage and current relation of the flux-controlled memristor could be expressed as

Figure

Cadence simulation results of the frequency-dependent pinched hysteresis loop operating at (a) 100 kHz, (b) 1 MHz, and (c) 5 MHz.

Figure

The proposed fully integrated programmable staircase function circuit is presented in Figure

The programmable staircase function circuit.

The digitally programmable MOS switch.

By controlling the switches S_{1}, S_{2}, and S_{3} in Figure _{1} and S_{3} are turned off, a stair is obtained (Figure _{2} is turned off, S_{1} and S_{3} are turned on and two stairs are obtained (Figure _{1}, S_{2}, and S_{3} are all turned on, three stairs are obtained (Figure _{2} is turned off, S_{1} and S_{3} are turned on; the simulated staircase function circuit with

The staircase function: (a)

The proposed fully integrated scroll-controllable hyperchaotic system is presented in Figure _{1}, OA_{2}, and OA_{4}) and two reverse proportional operators (OA_{3} and OA_{5}) in the fully integrated scroll-controllable hyperchaotic circuit. The circuit elements used in the chaotic circuit are

Proposed scroll-controllable hyperchaotic circuit.

From Figure

In order to explore the nonlinear dynamics of the fully integrated hyperchaotic system, the Lyapunov exponents and bifurcation diagrams are investigated using the MATLAB simulation results.

The dimensionless equations of the chaotic system could be expressed as

Let

Bifurcation diagram by adjusting

Lyapunov exponents by adjusting

The proposed fully integrated scroll-controllable hyperchaotic system is verified using the Cadence IC Design Tools 5.1.41 Spectre simulator with GlobalFoundries’ 0.18

The chip layout diagram of the chaotic oscillator is presented in Figure ^{2} including the testing pads. The Mentor Calibre software is used for the design rule check (DRC), layout versus schematic (LVS), and parasitic extraction (PEX) of the chaotic system. Based on the chip layout in Figure

Chip layout diagram of the chaotic circuit (1.8 mm^{2}).

The phase portrait in the _{2} is turned on, S_{1} and S_{3} are turned off).

The phase portrait in the _{2} is turned on, S_{1} and S_{3} are turned off).

The phase portrait in the _{2} is turned on, S_{1} and S_{3} are turned off).

The phase portrait in the _{1} and S_{3} are turned on, S_{2} is turned off).

The phase portrait in the _{1} and S_{3} are turned on, S_{2} is turned off).

The phase portrait in the _{1} and S_{3} are turned on, S_{2} is turned off).

The phase portrait in the _{1}, S_{2}, and S_{3} are all turned on).

The phase portrait in the _{1}, S_{2}, and S_{3} are all turned on).

The phase portrait in the _{1}, S_{2}, and S_{3} are all turned on).

When the switch S_{2} is turned on, S_{1} and S_{3} are turned off, a single-stair nonlinear staircase function is added in the chaotic system, and the simulation results are presented in Figures

Figures

When the switches S_{1} and S_{3} are turned on, S_{2} is turned off and a two-stair nonlinear staircase function is added in the chaotic system, and the simulation results are presented in Figures

Figures

When the switches S_{1}, S_{2}, and S_{3} are all turned on, a three-stair nonlinear staircase function is added in the chaotic system, and the simulation results are presented in Figures

Figures

Obviously, by using programmable switches in the staircase circuit, it is easy to generate controllable scrolls in the proposed fully integrated scroll-controllable hyperchaotic system.

This work proposed a novel fully integrated memristor-based scroll-controllable hyperchaotic system. The chaotic system is verified via bifurcation diagram and Lyapunov exponents. In addition, the new chaotic system is realized using the designed OA and multiplier and simulated using Cadence IC Design Tools with the GlobalFoundries’ 0.18

The data used to support the findings of this study are available from the corresponding author upon request.

The authors declare that there is no conflict of interests regarding the publication of this paper.

This work is supported by the National Natural Science Foundation of China (no. 61561022), the Natural Science Foundations of Hunan Province (2017JJ3254), the Education Department of Hunan Province project (nos. 16B212 and 15C0550), and the Doctoral Scientific Research Foundation of Jishou University under Grant jsdxxcfxbskyxm07.

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