Series resistance effect on the output parameters of buried emitter silicon solar cells

A realistic distributed equivalent circuit for the buried emitter silicon solar cell is presented 
taking into consideration the carriers paths through the planar and vertical junctions. In addition, a new 
theoretical model for the cell characteristics including the cell's mismatching, series resistance, different 
junctions (planar and vertical) and junctions geometry is considered in this work. The results are compared 
with the published data.


INTRODUCTION
Since the efficiency is an important economical factor in photovoltaic arrays, making higher efficiency silicon solar cells-at no higher cost-is an important way of making energy production by solar cells more competitive [1][2][3][4][5]. The multijunction cells have better efficiency than that obtained in conventional cells [2] due to their high internal quantum efficiency. The Buried Emitter Solar Cell (BESC) proposed by Bouazzi et al. [1] is presented in Figure 1 which is consisted of planar and vertical junctions. The vertical junction is potentially a more efficient device compared to the conventional junction (planar) due to its high collection at different wavelengths and high radiation resistance [6][7][8][9][10][11].
One of the important ways for achieving high efficiency for the solar cell is to reduce the effect of the series resistance. The different series resistance components come from semiconductor bulk, metal bulk, contact resistance, and lead connections [12].
The modeling of the BESC performance was investigated in different works [1,2,13] . In [1], the effects of the loading between the cells and the series resistance are neglected and as a consequence, an overestimated performance for the cell was obtained. On the other hand, a proposed model taking into consideration the effect of the internal loading was presented in [2] but still a little bit far from the realistic performance. In this work, we propose a new theoretical model for BESC performance considering the effects of the internal loading and the series resistance and in addition, the effect of the planar and vertical junctions. The effects of the series resistance and the internal mismatching on the different current components of the different junctions and their relations to the different cell's thickness are studied.

ANALYSIS
A cross-section area for the proposed symmetrical BESC structure is shown in Figure 1  the P+ layer in the Z-direction and as a consequence the generated carriers can be collected by the planar and vertical junctions in each cell. The total output current from each cell is a summation of the different current components from the different junctions. It is clear from Figure 1 that the four different cells are connected in parallel, so the total current from the whole cell is a summation of the currents from each cell. To get an expression for the current in each cell, we have to solve the carriers continuity equation for each cell with suitable boundary conditions [2,6,7,14]. It was solved for planar junctions [2] but for the vertical junction, the continuity equations [7,8] are: where n(x) is the electron minority carrier in P-type, p(x) is the hole minority carrier in n-type, D n is the electron diffusion constant, D p is the hole diffusion constant, τ n is the electron lifetime, τ p is the hole lifetime, N(λ) is the spectral transmitted photons number, and α(λ) is the silicon absorption coefficient.
The above two equations can be solved by certain boundary conditions to get an expression for the current in the vertical junctions. The short circuit current (I sc ) equation [6] is as follows, where W 1 is the P layer width, W 2 is the n layer width, λ 0 equals 1.1 unit for silicon, where L n is the electron diffusion length in P-type, L p is the hole diffusion length in n-type where h 1 is the depth of the P-layer (in case of cell 1) The saturation current of the vertical junction is: where n i is the intrinsic concentration, N A is the acceptor concentration, N D is the donor concentration. Therefore, the current-voltage equation is where v is the applied voltage and R s is the series resistance.
All the required data about the silicon (doping, resistivity, lifetime, …) was taken from [1,7,15]. In addition, the surface area is 1 cm 2 , the cell breadth is taken as 1 cm and the front surface recombination velocity is 10 4 cm/sec. In this work, we study the cell performance at two values for the first cell thickness (h 11 ) which are 3.5 µm and 7.5 µm. The value of the series resistance is estimated for the case of planar junctions and is calculated for the case of vertical junctions from the circuit diagram shown in Figure 2 [16,17].

RESULTS AND DISCUSSION
The whole BESC structure shown schematically in Figure 1 consists of one planar junction and two vertical junctions for each cell. A distributed equivalent circuit model illustrated in Figure 2 is used to describe the complicated junctions' geometry. The circuit diagram is composed of parallel and series branches representing the planar and vertical junctions. Due to the device dimensions, the equivalent circuits are distributed  and lumped for planar and vertical junctions respectively. A distributed resistors for the interface between the metal and the semiconductor (R I ) and metal strip (R A and R B ) are considered in the circuit. Table 1 summarize the output currents (I P and I V ) from planar and vertical junctions for each cell at different thickness h 11 . In both thickness values, I P decreases moving from cell 1 to cell 4 due to the reduction in the carriers generation. The same behavior for I V has been obtained except cell 2 at h 11 of 3.5 µm. In case of h 11 of 3.5 µm, although cell 1 has a higher generation rate and lower thickness compared to cell 2, the I V of cell 2 is bigger than the I V of cell 1 due to its higher collection with the bigger thickness. On the other hand, in case of h 11 equals 7.5 µm, cell 2 has a lower thickness and generation rate than the corresponding values for cell 2 in case of h 11 equals 3.5 µm, therefore the current I V decreases moving from cell1 to cell 2. It is clear, from Table 1, that the ratio (I V /I P ) for each cell varies from 7% to 15%.   series resistance (R s ) of cell 1 and cell 4 is around 0.15 Ω and for cell 2 and cell 3 is about 0.18 Ω. Figure 4 presents the I-V characteristics for the whole cell (case a and b) taking into consideration planar and vertical junctions. For cell a and b, R s has a value of 0.41 Ω and 0.38 Ω respectively. The difference between the two resistance values can be considered as a result of changing of the mismatching factor due to the changing of h 11 from 3.5 µm to 7.5 µm. In addition, the efficiency values are 13.83% and 14.81% for cell a and cell b. For h 11 of 3.5 µm, the published short circuit current (I sc ) values for BESC in [1,2] are 46.91 mA and 36 mA respectively. The reduction in I sc [2] is due to considering the internal loading effect. The calculated value for I sc from our model taking into consideration the effects of both planar and vertical junctions and the series resistance is 40.62 mA. Our calculated efficiency is 13.83% compared to an efficiency of 12.43% in case of considering the whole cell as planar junction only as mentioned in [2]. Therefore, an increase of 10% in the theoretical efficiency could be gained.

CONCLUSION
A new theoretical model for the performance of the BESC taking into consideration the effects of the planar and vertical cell's junctions and series resistance is proposed. A realistic distributed equivalent circuit for the whole cell is presented in this work. The calculated results are compared with the previous published data. There is an increase in the efficiency by about 10% due to the effects of vertical junction on the cell's characteristics and the series resistance.