Journal of Applied Mathematics

Volume 2013 (2013), Article ID 291410, 8 pages

http://dx.doi.org/10.1155/2013/291410

Research Article

Efficient Algorithms for Optimal 4-Bit Reversible Logic System Synthesis

Zhiqiang Li,¹ Hanwu Chen,² Guowu Yang,³ and Wenjie Liu⁴

¹College of Information Engineering, Yangzhou University, Yangzhou 225009, China

²School of Computer Science and Engineering, Southeast University, Nanjing 211189, China

³University of Electronic Science and Technology Chengdu, Sichuan, Chengdu 611731, China

⁴Nanjing University of Information Science & Technology, Nanjing 210044, China

Received 8 February 2013; Accepted 23 February 2013

Academic Editor: Xiaoyu Song

Copyright © 2013 Zhiqiang Li et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

Owing to the exponential nature of the memory and run-time complexity, many methods can only synthesize 3-bit reversible circuits and cannot synthesize 4-bit reversible circuits well. We mainly absorb the ideas of our 3-bit synthesis algorithms based on hash table and present the efficient algorithms which can construct almost all optimal 4-bit reversible logic circuits with many types of gates and at mini-length cost based on constructing the shortest coding and the specific topological compression; thus, the lossless compression ratio of the space of -bit circuits reaches near . This paper presents the first work to create all 3120218828 optimal 4-bit reversible circuits with up to 8 gates for the CNT (Controlled-NOT gate, NOT gate, and Toffoli gate) library, and it can quickly achieve 16 steps through specific cascading created circuits.

1. Introduction

Quantum computer is equivalent to quantum Turing machine, and quantum Turing machine is equivalent to a quantum logic circuit. Therefore, the quantum computer can be constructed by cascading and combining the quantum logical gates. Nowadays, many kinds of reversible quantum gates have been proposed, for example, CNOT gate [1], Toffoli gate, and Fredkin gate [2]. How to automatically construct the quantum circuit at small cost using given quantum gates? Several approaches for reversible logic circuit synthesis have been presented. Song et al. [3] presented algebraic characteristics of reversible gates. Iwama et al. [4] introduced transformation rules for CNOT-based circuits. Miller et al. [5] gave a synthesis method based on truth table and used template technology to simplify the circuit. Mishchenko and Perkowski [6] proposed a Reed Muller-based algorithm for optimizing quantum circuit. Gupta et al. [7] also gave a heuristic algorithm based on Reed Muller; Li et al. [8] proposed a general template algorithm. Shende et al. [9, 10] reduced the synthesis for reversible logic circuit to permutation and gave an effective recursive algorithm. Then, Yang et al. [11] reduced the synthesis for reversible logic circuit to group theory and presented a novel algorithm based on group-theory algebraic software GAP, while its performance was better than most others. Until today, we have not found a general and effective algorithm for multivariable quantum circuit synthesis. Owing to the exponential nature of the memory and run-time complexity, many existing methods can only synthesize 3-bit reversible circuits, and they perform only four steps for the CNP library in 4-bit circuit synthesis with mini-length for memory overflow [11–13], however, [14–16] are able to achieve 12 steps by using an enhanced bidirectional synthesis approach. We mainly absorb the ideas of our efficient 3-bit synthesis algorithms based on hash table and present the novel and efficient algorithms which can construct almost all optimal 4-bit reversible logic circuits [17]. Using lossless compression and cascading created circuits, our algorithms can get all the mini-length circuits whose lengths range from 0 to 8 with numbers 1, 28, 576, 9886, 147841, 1986374, 24375385, 274500662, and 2819198076, respectively; it can synthesize all the optimal 16-gate mini-length circuits for the CNT library.

2. Background

Definition 1. Let be a finite set; then, a permutation of is a bijection . If , is an permutation. Normally, the permutation of group theory begins from one, but our program in c++ can work well if the permutation contains zero. Let , and a permutation . It can be denoted as the cyclic form; for example, , ; that is, , , and is the identity permutation of , such that for any permutation of .

The reversible function can be described by permutation or truth table. The 3-bit reversible logic circuit in Figure 1 can be described by the permutation or the truth table in Table 1, where the input or output is and , respectively. Let the permutations of NOT gate, Toffoli gate, and CNOT gate be , , ; then, .

Table 1: True table.

Input
Output

0
0
0
0
2
0
1
0

1
0
0
1
6
1
1
0

2
0
1
0
0
0
0
0

3
0
1
1
1
0
0
1

4
1
0
0
7
1
1
1

5
1
0
1
3
0
1
1

6
1
1
0
5
1
0
1

7
1
1
1
4
1
0
0

Figure 1: Quantum reversible logic circuit.

In order not to repeat explanation, the following definitions are given.

(1)Let be any -bit reversible logic circuit with length ; it is a cascade of quantum gates , denoted by .(2)Let , , and .(3)For permutation , there are kinds of permutations, which are denoted by , respectively.(4)Let be the permutation of quantum gate ; then, the permutation of circuit is .(5)Let be the cost of quantum circuit and be the cost of quantum gate .(6)All the circuits in the paper are the reversible logic circuits.

Because permutation is often used in our algorithms, the effective expression of permutation is very important to improve the algorithms. Thus, we present the shortest coding scheme with saving plenty of space, which maps a permutation to an integer with the fewest bytes.

Definition 2. Let be ordinal number of in sequence ; then, it is the number of members which are both smaller than and before ; that is,

Ordinal numbers of all members in the sequence construct ordinal number sequence: , and obviously and . For example, the ordinal number sequence of is .

Lemma 3. The ordinal number of in Definition 2 can also be defined as

Proof. From (1), is the number of members which are both smaller than and before , and is the number of members which are both smaller than and after ; so, the sum of them is the number of members which are smaller than in the sequence .

Theorem 4. One can get the ordinal number sequence in Definition 2 by comparison times merely.

Proof. The comparison times using (1) and Lemma 3 are and for computing , respectively, and comparison times are all for computing ordinal number sequence. These two formulas can be chosen depending on condition to reduce the comparisons times. We use (1) if ; that is, , and use Lemma 3 if ; that is, . So, our method is that using (1) when is in the first half part of the sequence, and otherwise using Lemma 3, their comparison times are and , respectively. Finally, the whole comparison times are ; it is lesser than the half of .

Definition 5. The shortest coding of the permutation is .

Lemma 6. If the ordinal number sequences of two permutations are the same, then the two permutations must be also the same.

Proof. Suppose that we get any two permutations of the set , , and ; if their ordinal number sequences are all , then we will prove that ; namely, for all , .

Proof by Mathematical Induction

Basis. Clearly, , ; then, has elements which are lesser than ; that is, is th small element in . Similarly, is th small element in , and so ; that is, for .

Inductive Assumption. Let for .

Inductive Step. When , , and has elements which are both lesser than and before ; that is, is th small element in , and let , ; then ; that is, is ()th small element in . Similarly, is th small element in . Now, using the inductive assumption, we get ; that is, , and so ; thus, for .

Lemma 7. The coding function Code maps each ordinal number sequence to a distinct coding.

Proof. Let ; that is, the function Code maps ordinal number sequence to coding , and so the remainder is when is divided by 2, the quotient is , and the remainder is when this quotient is divided by 3. Follow the same steps; the recursive formula is , , , . Clearly, the coding function Code maps each ordinal number sequence to a distinct coding, and vice versa; so, it is a one-to-one correspondence between each coding and ordinal number sequence.

Theorem 8. The function Code is the shortest coding function.

Proof. different elements in totally have permutations. According to Lemma 6, two different ordinal number sequences corresponding to two permutations must be different, and according to Lemma 7, coding function Code maps each ordinal number sequence to a distinct coding. So, the codings of all permutations are different.

By Definition 5, , , , . So, the number of all codings is . There are different elements in corresponding to different coding, and thus the minimum number of all the codings is . Therefore, the function Code is the shortest coding function.

The subject of topology is concerned with those features of geometry which remain unchanged after twisting, stretching, or other deformations of a geometrical space; any continuous change which can be continuously undone is allowed, but cannot be broken.

Definition 9. Line permutation is the operation which permutes quantum lines in quantum circuit without break. Obviously, it is a specific topological transformation. Let be quantum gate being operated by line permutation . The circuit , operated by line permutation , is .

For example, in Figure 2, quantum circuit is operated by line permutation , where .

Figure 2: The line permutation of quantum circuit.

The circuit after applying topological transformation can be simplified, because the gate's function cannot be changed when the order of its same kind of points is changed.

Consider . If there are basal gates in quantum gate library , , and , then , and the set of all permutations of the gates in is .

The set of all circuits of operated by line permutation is denoted by .

Definition 10. Direction transform (Figure 3) has two kinds of operations, obverse direction transform and reverse direction transform. It is also a specific topological transformation; the obverse direction transform of gate is denoted by . Thus, , . Gate is symmetric, if , and otherwise it is asymmetric. Let circuit , and the two gates are symmetric; then, .

Figure 3: The direction transform of quantum circuit.

Consider . , if all the gates in are symmetric. Direction transform can be used in our synthesis algorithms only if all quantum gates are symmetric or their inverse gates are all in the quantum gate library.

The set of all circuits of operated by direction transform is denoted by .

From Definitions 9 and 10, the following properties can be gotten.

Property 1. and , but , where denotes the circuit being operated by line permutation and line permutation ; so, . , and thus . Normally, ; hence, .

Property 2. , where denotes the circuit being operated by direction transform and direction transform . The circuit is not changed, if , and otherwise, it is operated by reverse direction transform; thus, . In the same way, .

Property 3. , where denotes the circuit being operated by line permutation and direction transform , and denotes that the circuit is operated by direction transform and line permutation . Line permutation is vertical transform, and direction transform is horizontal transform; so, the order of the two operations does not affect their compound function, and thus .

We show by Properties 1, 2, and 3 that the order of the previous topological transformations except the line permutations in quantum circuits can not affect their compound functions.

Lemma 11. For all , for all , .

Proof. Consider any quantum gate , operated by any line permutation , whose type is not changed so, . When any quantum circuit is operated by any direction transform, its direction may be changed, but its cost can not be changed; thus, for all , , and then , where of optimal should be minimal with the cost function. If for all , , then ; that is, the length of is minimal, and thus minimum cost standard degenerates to mini-length standard.

Lemma 12. Any optimal circuit after any specific topological transformation must be optimal.

Proof. Let the circuit be optimal, and circuit . Assume that circuit is not optimal, and so there is an optimal circuit with and ; thus, . Let circuit ; by the Lemma 11, there is , and , . Thus, ; that is, the functions of circuit and circuit are the same, but is more optimal than in contradiction to being optimal.

Lemma 13. By Definition 9, for all , .

Proof. By permutation group theory, for all , , and , and thus for all , , , . Similarly, we have

For all , = = = .

Definition 14. Let be a circuit, , and thus , , . Let ; is the minimal permutation circuit of . All circuits gotten by all the specific topological transformations of compose the set . The function returns the minimal permutation , line permutation and direction transform , where .

Theorem 15. From Definition 14, is a circuit of , and can be gotten only by ; that is, the lossless compression ratio of the space is near .

Proof. Obviously, all the minimal permutation circuits of must be , . Let be the set of all circuits gotten by all the specific topological transformations of ; thus, = = , where , ; that is, , and few specific topological transformation circuits may be the same. Thus and . Then, the lossless compression ratio of the set is near .

Let be an -bit quantum gate library with gates , and a set of all -bit reversible circuits synthesized by any gates in . For example, . The average compression ratio of , whose circuits are synthesized 8 layers at minimal cost, is 47.95.

Given two quantum logic circuits, and , , , .

Taking all specific topological transformations of a 3-bit circuit as an example, there are kinds of transformations. In Table 2, the bidirectional arrow expresses exchanging the two quantum lines, and the minimal permutation circuit of all circuits is circuit by computing coding.

Table 2: All the specific topological transformations of 3-bit logic circuit.

Line permutation
Obverse direction
Coding
Reverse direction
Coding

23759

28679

25199

34439

11951

16985

8949

18903

14975

32969

9333

29241

The way of computing the shortest coding of circuit in Table 2 is given.

(1)By Definition 1, the permutation of circuit is .(2)By Definition 2, the ordinal number sequence of is . (3)By Definition 5, the shortest coding is 23759.

Definition 16. Given two circuit sets and , the set of all circuits of cascaded by all circuits of is denoted by .

Lemma 17. Given two circuit sets and , .

Proof. By Definition 16, , thus = = = = .

Theorem 18. Given the set of all optimal circuits with length , .

For saving memory, we only store minimal permutation circuits . The common computing method is that, firstly, can be gotten by decompressing , secondly, can be gotten by , and lastly, can be gotten by compressing . Its number of decompressing circuit is , but ours is zero based on Theorem 15. The number of cascading circuit and the number of compressing circuit in the common method all are times than ours; so, our method is better.

3. New Synthesis Algorithm

A quantum logic gate realizes certain permutation in essence; quantum circuit is the cascade of some quantum gates, and so the basic function of quantum circuit can be represented the multiplication of permutations. The basic idea of the hash-based 3-bit synthesis algorithm which we previously advanced is constructing an optimal circuit using WFS, making a one-to-one correspondence between the elements in the hash table and different circuits. Thus, we need only one step to check whether the circuit of the same function has already been found to decide whether it is optimal. But it is unfeasible if we use this algorithm directly in 4-bit circuit synthesis, since the length of the hash table is at least ; so, it is extremely memory consuming. Otherwise, if we use DFS, it will be meaningless that the algorithm runs too slowly or can not realize optimal. To sum up, we adopt the BFS, with higher speed and more synthesis capability, and some lossless data compression methods to reduce memory consumption.

(1)Represent the permutation using the shortest encoding. Only bits is required to represent 4-bit circuit permutations using the permutation encoding method in Definition 5, rather than 64 bits as usual.(2)Compress the optimal circuits without loss. Using line permutation alone, nearly times compression can be reached, while using both line permutation and direction transformation, nearly times compression can be reached, which is the backbone of this paper.(3)Use hash table with length in the top of the data structure, with each element pointing to a different RB tree in Figure 4 and each node in the tree reduces 2 bytes. Hash table and RB tree always remain effective, and RB tree can also allocate the memory dynamically. Therefore the data structure can not only permit a faster access speed, but also save memory space.

Figure 4: The data structure of the minimal permutation circuit with length .

How to determine the length of hash table? Let the permutation of -bit circuit be , whose shortest coding is , in binary. Use the rear bits as the hash address, the rest bits as the value of the nodes in the RB tree. Suppose that the length of the elements in hash table is bytes; so, hash table uses bytes while the RB tree saves bytes, and the maximum space this structure saves is . Take the 4-bit circuit based on CNT quantum gate library as an example; each element in hash table is a pointer pointing to the different tree, taking 4 bytes. The number of minimum permutation circuits with length 8 is 58777916, when , and the maximum of the function is ; so, the optimal length of hash table is .

In this paper, we use BFS to get all the first layers of optimal circuits. If the gate library is determined, then the optimal circuits are determined. In order to save time, we store all minimum permutation circuits in the first layers in a file. If CNT gate library is used, then , and we get a 700 MB file. As there are considerable gates in the 4-bit circuit quantum gate library, thus lots of optimal circuits are generated at each length. When a circuit reaches a certain length, the memory will overflow, and so has practical upper lower limit related to memory. After the lossless compression mentioned earlier, only the minimum permutation circuits are stored, saving 47.95 times less of circuits. The length of the overall synthesis circuits reaches 8 instead of 6, 117.7 times larger; the synthesizable length grows form 12 to 16 [14].

3.1. Minimal Length Algorithm

The node type of our RB tree is defined as follows:

struct rbtnode {

         gate; // the gate is in the end of the circuit          cpm; // the permutation of the circuit Min()         binv; // the current circuit is inverted or not         lnpm; // Min(()) ≡ GetMin((); binv; lnpm)         pcpm; // the permutation of the previous circuit         pbinv; // the previous circuit is inverted or not

}

To enhance readability, two ways are used to simplify the algorithms.

(1)All permutations are not transformed into the relevant shortest codings. (2)The hash table in the top of Figure 4 is omitted, and all the minimum permutation circuits in each layer are only saved in a RB tree; for example, is the RB tree which has saved all minimum permutation circuits with length .

3.2. Algorithm for the Minimal Permutation Quantum Reversible Logic Circuits Representation in QML

For more details, see Algorithm 2.

3.3. General Algorithm for the Quantum Reversible Logic Circuits Representation in QML (Algorithm 1)

Input: Quantum Gate Library

Output: 

1:

2: while   do

3:    

4:    for each node Node x in  do

5:        

6:        for   do

7:            if   then

8:                

9:            end if

10:          for each gate in  do

11:                

12:                if   then

13:                    

                                                ,

14:                    if memory overflow error then

15:                        

16:                    end if

17:                end if

18:            end for

19:        end for

20:    end for

21:    

22: end while

23:

Algorithm 1: Quantum_Minimum_Length (QML).

Input: Quantum Gate Library , minimal permutation ,

            circuit length

Output: Circuit of minimal permutation with mini-length

1: compute as in for the first time;

2: .

3: .

4: while   do

5:    

6:    .

7:    .

: end while

9: ..

10: .

11: for  to  do

12:    ..

13:    ..

14:    

15: end for

16: return 

Algorithm 2: Minimal_Quantum_Representation (MQR).

For more details, see Algorithm 3.

Input: Quantum Gate Library , permutation

Output: Circuit of permutation with mini-length

1: if   then

2:    

3:    return 

4: else if  

    ,

        then

5:    

6:    

7:    

8:    return 

: else

:    return 

: end if

Algorithm 3: Quantum_Minimum _Representation (QMR).

4. Experimental Results

Our experiments were conducted using many benchmark functions for 4-bit reversible logic circuits synthesis, and [14, 15] dealt with the synthesis of 4-qubit circuit for the high complexity of the algorithm. Based on CNP quantum gate library, using the mini-length as criteria, [14] added 4 layers in the basis of [11] through bidirection synthesis, and another 4 layers by combining DFS, thus realized a 12 layers synthesis of arbitrary circuits. Yet [14] can only synthesize the first 4 layers of the optimal circuit at a time, while in our previous study, for example, the hash-based 3-bit synthesis algorithm, the average speed of the mini-length and minimum cost are 49.15 and 365.13 times of [11], respectively. In this paper, we used CNT quantum gate library and mini-length criteria, creating all optimal circuits with up to 8 gates. By bidirection cascading the generated circuits, we can quickly synthesize the optimal quantum circuits within the length of 16, without consuming more memory. Our bidirection cascading is quite different with the bidirection synthesis used in [14]; they calculated the head and tail of the circuit, respectively, then moved forward to the middle. In order to avoid repeated computation, we first synthesize the former parts of the circuit, then perform specific topology transformations on them and reuse them in the latter part.

To evaluate the ability of the algorithm while synthesizing complicated circuits, we have run our program on a great number of circuits, and none of them has been found not to be synthesized. Then, we only give two examples. We cascaded the two optimal circuits 4_49 and Hwb4 to get one circuit in Figure 5 A. By using the generated all minimal permutation circuits with up to 8 gates, it took only 35 s to generate circuit B. It is easy to prove that the permutation of both A and B are (15,2,3,12,5,9,1,11,0,10,14,6,4,8,7,13). Synthesized Alhagi01 (2,12,8,13,0,9,6,15,10,11,14,4,5,3,1,7) circuit is given in Figure 6.

Figure 5: The 4-bit reversible logic circuits synthesis.

Figure 6: Alhagi01 circuit synthesis.

5. Conclusions

Based on the idea that the synthesis of reversible logic circuit is a permutation problem in essence, we present the novel and efficient quantum circuit synthesis algorithms. Among them, we elaborately construct a shortest encoding method of the permutation and compress the memory space of the -bit optimal circuits to times less using certain topology transformation of quantum circuits. By bidirectional cascading of the generated optimal circuits, using several quantum gates and the mini-length cost metric, our algorithms can efficiently generate most optimal 4-bit reversible logic circuits.

Acknowledgments

This research was supported by the National Natural Science Foundation of China (nos. 61070240, 61170321, 61272175, and 61103235), the Natural Science Foundation of College of Jiangsu Province (no. 10KJB520021), and Specialized Research Fund for the Doctoral Program of Higher Education (no. 20110092110024).

References

R. P. Feynman, “Quantum mechanical computers,” Foundations of Physics, vol. 16, no. 6, pp. 507–531, 1986.

E. Fredkin and T. Toffoli, “Conservative logic,” International Journal of Theoretical Physics, vol. 21, no. 3-4, pp. 219–253, 1982.

X. Song, G. Yang, M. Perkowski, and Y. Wang, “Algebraic characterization of reversible logic gates,” Theory of Computing Systems, vol. 39, no. 2, pp. 311–319, 2006.

K. Iwama, Y. Kambayashi, and S. Yamashita, “Transformation rules for designing CNOT-based quantum circuits,” in Proceedings of the 39th Annual Design Automation Conference (DAC '02), pp. 419–424, New Orleans, La, USA, June 2002.

D. M. Miller, D. Maslov, and G. W. Dueck, “A transformation based algorithm for reversible logic synthesis,” in Proceedings of the 40th Design Automation Conference, pp. 318–323, San Jose, Calif, USA, June 2003.

A. Mishchenko and M. Perkowski, “Logic synthesis of reversible wave cascades,” in Proceedings of 11th IEEE International Workshop on Logic Synthesis, pp. 197–202, New Orleans, La, USA, 2002.

P. Gupta, A. Agrawal, and N. K. Jha, “An algorithm for synthesis of reversible logic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 11, pp. 2317–2330, 2006.

W. Li, H. Chen, and Z. Li, “Application of semi-template in reversible logic circuit,” in Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design (CSCWD '07), pp. 332–336, Melbourne, Australia, April 2007.

V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, “Reversible logic circuit synthesis,” in IEEE/ACM International Conference on Computer Aided Design (ICCAD '02), pp. 353–360, San Jose, Calif, USA, November 2002.

V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes, “Synthesis of reversible logic circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 710–722, 2003.

G. Yang, X. Song, W. N. N. Hung, M. A. Perkowski, and C.-J. Seo, “Synthesis of reversible circuits with minimal costs,” Calcolo, vol. 45, no. 3, pp. 193–206, 2008.

G. Yang, X. Song, and M. Perkowski, “Fast synthesis of exact minimal reversible circuits using group theory,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '05), vol. 2, pp. 18–21, Shanghai, China, 2005.

W. N. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, “Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 9, pp. 1652–1663, 2006.

G. Yang, X. Song, W. N. N. Hung, and M. A. Perkowski, “Bi-direction synthesis for reversible circuits,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), pp. 14–19, Tampa, Fla, USA, May 2005.

G. Yang, X. Song, W. N. N. Hung, and M. A. Perkowski, “Bi-directionalsynthesis of 4-bit reversible circuits,” Computer Journal, vol. 51, no. 2, pp. 207–215, 2008.

G. Yang, F. Xie, W. N. N. Hung, X. Song, and M. A. Perkowski, “Realization and synthesis of reversible functions,” Theoretical Computer Science, vol. 412, no. 17, pp. 1606–1613, 2011.

Z. Li, H. Chen, B. Xu, and W. Liu, “Fast algorithm for 4-qubit reversible logic circuits synthesis,” in Proceedings of the IEEE Congress on Evolutionary Computation (IEEE World Congress on Computational Intelligence) (CEC '08), pp. 2202–2207, Hongkong, China, 2008.